/********************************************************************************
 * FILE NAME: MPC5777M.h                     COPYRIGHT (c) Freescale 2013       * 
 * REVISION:  1.0                                     All Rights Reserved       *
 *                                                                              *
 * DESCRIPTION:                                                                 *
 * This file contains all of the register and bit field definitions for         *
 * the Matterhorn.                                                              *
 *==============================================================================*
 * UPDATE HISTORY                                                               *
 * REV      AUTHOR      DATE       	DESCRIPTION OF CHANGE                       *
 * ---   -----------  ---------    	---------------------                       *
 * 0.2      P.A.      21-Mar-12     Adding register array style                 *
 *                                                                              *
 * 0.3      P.A.      05-Apr-12     Adding new modules sent by Curt             *
 *                                  Hillier                                     *
 *                                                                              *
 * 0.4      P.A.      25-Jul-12     Adding latest modules.                      *
 * 0.4A     C.H.      13-Aug-12     Corrected errors in memory map.             *
 *                                                                              *
 * CGM was incorrectly generated at 0UL.  Corrected to 0xFFFB0700UL             *
 * FR_0 was incorrectly generated at 0xFC250000UL.  Corrected to 0xFFE50000UL   *
 * LFAST was incorrectly generated at 0x1UL.  Corrected to 0xFFFD8000UL         *
 * PRAMC was incorrectly generated at 0UL.  Correct to 0xFC020000UL.            *
 *                                                                              *
 * 0.4b to                                                                      *
 *  0.5b    C.H.      22-Oct-12     Interim builds for debugging.               *
 * 0.5c     C.H.      23-Oct-12     replace autogenerated SARADC                *
 *                                  block with McKinley.  Too many mis-         *
 *                                  matches present.                            *
 *                                  Collapse DSPI CTARs to array                *
 * 0.5d     C.H.      24-Oct-12     Incorporate feedback from PE.               *
 *                                    add #ifdef support for SARADC arrays      *
 *                                    add array support for MC_ME_RUN_MC        *
 * 0.6      C.H.      26-Oct-12     MC_CGM uses base address of 0xFFFB_0700     *
 *                                  and registers offsets starting at 0x0700.   *
 *                                  This results in incorrect absolute          *
 *                                  addresses starting at 0xFFFB_0E000.         *
 *                                  To fix this, commented out the reserved     *
 *                                  space "//  uint8_t MC_CGM_reserved0[1792];" *
 *                                  and keep module base address = 0xFFFB_0700. *
 *                                  This matches McKinley implementation.       *
 *                                                                              *
 * 0.7      M.D.      05-Mar-13     Updated to RDP from Jan 2013 as follows:    *
 *                                  Module INTC: Added register MPROT           *
 *                                  And updated structure of PSR register       * 
 *                                  Module MCAN: Updated registers NDAT1,       *
 *                                  NDAT2, RXFOS, RXF1S, TXFQS, TXEFS           *
 *                                  Also added some comments to Module MCAN     *
 *                                                                              *
 * 0.8      M.D.      13-Mar-13     Updated PRAMC & CRC from new XML drop       *
 *                                  Expanded AC0_DC[5] register                 *
 *                                  Change to PRAMC was manually inserted as    *
 *                                  code generated from XML was not correct     *  
 *                                  MC_ME: Inserted hand coded PCTL11 & 15      *
 *                                  due to missing from XML                     *
 *                                                                              *   
 * 0.9      M.D.      25-Jul-13     Updated from new XML drop                   *
 *                                                                              *
 * 1.0      M.D.      17-Oct-13     Updated from RDP rev3                       *
 *                                                                              *
 * 1.01     C.H.      05-Nov-13     Fixed error in MC_CGM base address          *
 *                                                                              *   
 *==============================================================================*
 * COPYRIGHT:                                                             *
 *  Freescale Semiconductor, INC. All Rights Reserved. You are hereby     *
 *  granted a copyright license to use, modify, and distribute the        *
 *  SOFTWARE so long as this entire notice is retained without alteration *
 *  in any modified and/or redistributed versions, and that such modified *
 *  versions are clearly identified as such. No licenses are granted by   *
 *  implication, estoppel or otherwise under any patentsor trademarks     *
 *  of Freescale Semiconductor, Inc. This software is provided on an      *
 *  "AS IS" basis and without warranty.                                   *
 *                                                                        *
 *  To the maximum extent permitted by applicable law, Freescale          *
 *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,    *
 *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A      *
 *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD  *
 *  TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY     *
 *  ACCOMPANYING WRITTEN MATERIALS.                                       *
 *                                                                        *
 *  To the maximum extent permitted by applicable law, IN NO EVENT        *
 *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER    *
 *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,  *
 *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER         *
 *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.  *
 *                                                                        *
 *  Freescale Semiconductor assumes no responsibility for the             *
 *  maintenance and support of this software                              *
 *                                                                        *
 **************************************************************************/
/*>>>>>>> NOTE! this file is auto-generated please do not edit it! <<<<<<<*/

/**************************************************************************
 * Example register & bit field write:                                    *
 *                                                                        *
 *  <MODULE>.<REGISTER>.B.<BIT> = 1;                                      *
 *  <MODULE>.<REGISTER>.R       = 0x10000000;                             *
 *                                                                        *
 **************************************************************************/

//#define CUT1   // Define this if using MPC5777M Cut 1.
#ifndef _MPC5777M_H_
#define _MPC5777M_H_
#include "typedefs.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __MWERKS__
#pragma push
#pragma ANSI_strict off
#endif
#ifdef __ghs__
#pragma ghs nowarning 618
#endif


/* ============================================================================
   =============================== Module: AMU2 ===============================
   ============================================================================ */

struct AMU2_tag {
  uint8_t AMU2_reserved0[65536];
  struct {
    union {                            /* AMU ID and Version Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :15;
        vuint32_t CH:1;
        vuint32_t  :12;
        vuint32_t VER:4;
      } B;
    } IDV;
    uint8_t CHANNEL_reserved0[8];
    union {                            /* AMU N crossing Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t NMSK:16;
        vuint32_t NCRS:16;
      } B;
    } N;
    union {                            /* AMU P1 Pointer Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :17;
        vuint32_t PTR:13;
        vuint32_t  :2;
      } B;
    } P1PTR;
    union {                            /* AMU P2 Pointer Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :17;
        vuint32_t PTR:13;
        vuint32_t  :2;
      } B;
    } P2PTR;
    union {                            /* AMU P3 Pointer Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t PTR:30;
        vuint32_t  :2;
      } B;
    } P3PTR;
    union {                            /* AMU P4 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE32:32;
      } B;
    } P4;
    union {                            /* AMU P5 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE32:32;
      } B;
    } P5;
    union {                            /* AMU P6 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :16;
        vuint32_t UINT:16;
      } B;
    } P6;
    union {                            /* AMU P7 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :27;
        vuint32_t UINT:5;
      } B;
    } P7;
    union {                            /* AMU P8 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t THRHC:16;
        vuint32_t UINT:16;
      } B;
    } P8;
    union {                            /* AMU P9M Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE64:32;
      } B;
    } P9M;
    union {                            /* AMU P9L Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE64:32;
      } B;
    } P9L;
    union {                            /* AMU V Pointer Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t PTR:30;
        vuint32_t  :2;
      } B;
    } VPTR;
    union {                            /* AMU L Pointer Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :17;
        vuint32_t PTR:13;
        vuint32_t  :2;
      } B;
    } LPTR;
    union {                            /* AMU U Pointer Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :17;
        vuint32_t PTR:13;
        vuint32_t  :2;
      } B;
    } UPTR;
    union {                            /* AMU DMA Source Address Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t PTR:29;
        vuint32_t  :3;
      } B;
    } DSA;
    union {                            /* AMU DMA Destination Address Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :17;
        vuint32_t PTR:12;
        vuint32_t  :3;
      } B;
    } DDA;
    union {                            /* AMU DMA Transfer Count Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t THRHC:11;
        vuint32_t  :5;
        vuint32_t BCNT:13;
        vuint32_t  :3;
      } B;
    } DCNT;
    union {                            /* AMU DMA Checksum Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t UINT:32;
      } B;
    } DCKS;
    union {                            /* AMU DMA Control & Configuration Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t SRTSP:3;
        vuint32_t  :1;
        vuint32_t MAXSP:3;
        vuint32_t ADICFG:2;
        vuint32_t SARU:2;
        vuint32_t DARU:2;              /* Destination Address Register Update */
        vuint32_t HCRCE:1;
        vuint32_t ECRC:1;
        vuint32_t CADS:1;
        vuint32_t DECC:1;              /* Disable ADMA ECC single bit Corrections */
        vuint32_t STMP3:1;
        vuint32_t STMV32:1;
        vuint32_t STMV16:1;
        vuint32_t EHP:1;
        vuint32_t DSAS:1;
        vuint32_t STP:1;
        vuint32_t DEICFG:1;            /* ADMA Error Interrupt Configuration */
        vuint32_t WFDNI:1;
        vuint32_t WFS23D:1;
        vuint32_t WFS1D:1;
        vuint32_t RSM:1;
        vuint32_t  :1;
        vuint32_t FARZ:1;              /* Force ARAM to Zero */
        vuint32_t SRT:1;
      } B;
    } DCCR;
    union {                            /* AMU Control & Configuration 1 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t SRTSP:3;
        vuint32_t  :1;
        vuint32_t MAXSP:3;
        vuint32_t AEICFG:2;
        vuint32_t OVICFG:2;
        vuint32_t NCICFG:2;
        vuint32_t DNICFG:2;
        vuint32_t BPRI:1;
        vuint32_t EECC:1;
        vuint32_t DDSL:1;
        vuint32_t SETZ:1;
        vuint32_t ESTZC:1;
        vuint32_t  :2;
        vuint32_t V16:1;
        vuint32_t VFH:1;
        vuint32_t CMEXP:7;
      } B;
    } CCR1;
    union {                            /* AMU Control & Configuration 2 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t ADCCRE:1;
        vuint32_t ADCCR18:1;           /* Alternate AMU_DCCRCHn[STMP3] */
        vuint32_t ADCCR19:1;           /* Alternate AMU_DCCRCHn[STMV32] */
        vuint32_t ADCCR20:1;           /* Alternate AMU_DCCRCHn[STMV16] */
        vuint32_t  :4;
        vuint32_t ADCCR25:1;           /* Alternate AMU_DCCRCHn[WFDNI] */
        vuint32_t ADCCR26:1;           /* Alternate AMU_DCCRCHn[WFS23D] */
        vuint32_t ADCCR27:1;           /* Alternate AMU_DCCRCHn[WFS1D] */
        vuint32_t ADCCR31:1;           /* Alternate AMU_DCCRCHn[SRT] */
        vuint32_t  :1;                 /* Alternate AMU_DCCRCHn[SRT] */
        vuint32_t ENCRS:1;             /* Enable N Crossing event */
        vuint32_t SNCRS:1;
        vuint32_t CSXXS:1;             /* Clear Stage "X" Execution State */
        vuint32_t  :6;
        vuint32_t S23STP:1;            /* Stage23 Stop Request */
        vuint32_t  :1;
        vuint32_t WFSS23:1;
        vuint32_t WFDS23:1;
        vuint32_t WFDS1:1;
        vuint32_t S23RSM:1;
        vuint32_t  :1;
        vuint32_t S23SRT:1;
        vuint32_t S1SRT:1;
      } B;
    } CCR2;
    uint8_t CHANNEL_reserved1[32];
    union {                            /* AMU RES64M Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE64:32;
      } B;
    } RES64M;
    union {                            /* AMU RES64L Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE64:32;
      } B;
    } RES64L;
    union {                            /* AMU Status, Error & Interrupt Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t CHBSY:1;
        vuint32_t ADSTM:1;
        vuint32_t S23XS:2;
        vuint32_t S1XS:2;
        vuint32_t ADMAS:2;
        vuint32_t QDSL:1;
        vuint32_t ACURSP:3;
        vuint32_t  :1;
        vuint32_t DCURSP:3;
        vuint32_t YCAFLT:1;
        vuint32_t ZCAFLT:1;
        vuint32_t S23AFLT:1;
        vuint32_t S1AFLT:1;
        vuint32_t IDVERR:1;
        vuint32_t ADMERR:1;
        vuint32_t CKSERR:1;
        vuint32_t ECCERR:1;
        vuint32_t RGCERR:1;
        vuint32_t DEIRQ:2;             /* ADMA Error Interrupt Request */
        vuint32_t ADIRQ:1;
        vuint32_t ERIRQ:1;
        vuint32_t OVIRQ:1;
        vuint32_t NCIRQ:1;
        vuint32_t DNIRQ:1;
      } B;
    } SEIR;
    union {                            /* AMU Actual Checksum Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t UINT:32;
      } B;
    } ACKS;
    union {                            /* AMU RES32 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE32:32;
      } B;
    } RES32;
    union {                            /* Aliased Copy of AMU Status, Error & Interrupt Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t CHBSY:1;
        vuint32_t ADSTM:1;
        vuint32_t S23XS:2;
        vuint32_t S1XS:2;
        vuint32_t ADMAS:2;
        vuint32_t QDSL:1;
        vuint32_t ACURSP:3;
        vuint32_t  :1;
        vuint32_t DCURSP:3;
        vuint32_t YCAFLT:1;
        vuint32_t ZCAFLT:1;
        vuint32_t S23AFLT:1;
        vuint32_t S1AFLT:1;
        vuint32_t IDVERR:1;
        vuint32_t ADMERR:1;
        vuint32_t CKSERR:1;
        vuint32_t ECCERR:1;
        vuint32_t RGCERR:1;
        vuint32_t  :2;
        vuint32_t ADIRQ:1;
        vuint32_t ERIRQ:1;
        vuint32_t OVIRQ:1;
        vuint32_t NCIRQ:1;
        vuint32_t DNIRQ:1;
      } B;
    } ASEIR;
    union {                            /* Aliased copy of AMU Actual Checksum Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t UINT:32;
      } B;
    } AACKS;
    uint8_t CHANNEL_reserved2[4];
    union {                            /* AMU Y64M Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE64:32;
      } B;
    } Y64M;
    union {                            /* AMU Y64L Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE64:32;
      } B;
    } Y64L;
    union {                            /* AMU P8 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t THRHC:16;
        vuint32_t UINT:16;
      } B;
    } AP8;
    union {                            /* AMU Status, Error & Interrupt No Clear Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t CHBSY:1;
        vuint32_t ADSTM:1;
        vuint32_t S23XS:2;
        vuint32_t S1XS:2;
        vuint32_t ADMAS:2;
        vuint32_t QDSL:1;
        vuint32_t ACURSP:3;
        vuint32_t  :1;
        vuint32_t DCURSP:3;
        vuint32_t YCAFLT:1;
        vuint32_t ZCAFLT:1;
        vuint32_t S23AFLT:1;
        vuint32_t S1AFLT:1;
        vuint32_t IDVERR:1;
        vuint32_t ADMERR:1;
        vuint32_t CKSERR:1;
        vuint32_t ECCERR:1;
        vuint32_t RGCERR:1;
        vuint32_t  :2;
        vuint32_t ADIRQ:1;
        vuint32_t ERIRQ:1;
        vuint32_t OVIRQ:1;
        vuint32_t NCIRQ:1;
        vuint32_t DNIRQ:1;
      } B;
    } SEINC;
    union {                            /* AMU Y32 Channel n Register */
      vuint32_t R;
      struct {
        vuint32_t IEEE32:32;
      } B;
    } Y32;
    uint8_t CHANNEL_reserved3[76];
  } CHANNEL[2];
};


/* ============================================================================
   =============================== Module: C55FMC =============================
   ============================================================================ */

struct C55FMC_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t RVE:1;                 /* Read Voltage Error */
      vuint32_t RRE:1;                 /* Read Reference Error */
      vuint32_t AEE:1;                 /* Address Encode Error */
      vuint32_t EEE:1;                 /* ECC after ECC Error */
      vuint32_t  :12;
      vuint32_t EER:1;                 /* ECC Event Error */
      vuint32_t RWE:1;                 /* Read-While-Write Event Error */
      vuint32_t SBC:1;                 /* Single Bit Correction */
      vuint32_t  :1;
      vuint32_t PEAS:1;                /* Program Access Space */
      vuint32_t DONE:1;                /* State Machine Status */
      vuint32_t PEG:1;                 /* Program/Erase Good */
      vuint32_t PECIE:1;               /* Program/Erase Complete Interrupt Enable */
      vuint32_t FERS:1;                /* Factory Erase and Program */
      vuint32_t  :2;
      vuint32_t PGM:1;                 /* Program */
      vuint32_t PSUS:1;                /* Program Suspend */
      vuint32_t ERS:1;                 /* Erase */
      vuint32_t ESUS:1;                /* Erase Suspend */
      vuint32_t EHV:1;                 /* Enable High Voltage */
    } B;
  } MCR;

  union {                              /* Alternate Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t PEASa:1;               /* Program Access Space */
      vuint32_t DONEa:1;               /* State Machine Status */
      vuint32_t PEGa:1;                /* Program/Erase Good */
      vuint32_t  :4;
      vuint32_t PGMa:1;                /* Program */
      vuint32_t PSUSa:1;               /* Program Suspend */
      vuint32_t ERSa:1;                /* Erase Suspend */
      vuint32_t ESUSa:1;               /* Erase Suspend */
      vuint32_t EHVa:1;                /* Enable High Voltage */
    } B;
  } MCRA;

  union {                              /* Extended Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t HT:1;                  /* High Temperature Enabled. */
      vuint32_t  :2;
      vuint32_t n256K:5;
      vuint32_t n64Kh:3;
      vuint32_t n32Kh:2;
      vuint32_t n16Kh:3;
      vuint32_t n64Km:3;
      vuint32_t n32Km:2;
      vuint32_t n16Km:3;
      vuint32_t n64Kl:3;
      vuint32_t n32Kl:2;
      vuint32_t n16Kl:3;
    } B;
  } MCRE;

  uint8_t C55FMC_reserved0[4];
  union {                              /* Lock 0 register */
    vuint32_t R;
    struct {
      vuint32_t TSLOCK:1;              /* UTest NVM Lock. */
      vuint32_t  :1;
      vuint32_t LOWLOCK:14;            /* Low Block Lock */
      vuint32_t MIDLOCK:16;            /* Mid Block Lock */
    } B;
  } LOCK0;

  union {                              /* Lock 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHLOCK:16;           /* High Block Lock */
    } B;
  } LOCK1;

  union {                              /* Lock 2 register */
    vuint32_t R;
    struct {
      vuint32_t A256KLOCK:32;          /* 256 KB Block Lock */
    } B;
  } LOCK2;

  union {                              /* Lock 3 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t A256KLOCK:16;          /* 256 KB Block Lock */
    } B;
  } LOCK3;

  uint8_t C55FMC_reserved1[8];
  union {                              /* Alternate Lock 0 register */
    vuint32_t R;
    struct {
      vuint32_t TSLOCKa:1;             /* Alternate UTest NVM Lock. */
      vuint32_t  :1;
      vuint32_t LOWLOCKa:14;           /* Alternate Low Block Lock */
      vuint32_t MIDLOCKa:16;           /* Alternate Mid Block Lock */
    } B;
  } LOCK0A;

  union {                              /* Alternate Lock 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHLOCKa:16;          /* Alternate High Block Lock */
    } B;
  } LOCK1A;

  uint8_t C55FMC_reserved2[8];
  union {                              /* Select 0 register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t LOWSEL:14;             /* LOW Block Select. */
      vuint32_t MIDSEL:16;             /* Mid Block Select. */
    } B;
  } SEL0;

  union {                              /* Select 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHSEL:16;            /* High Block Select. */
    } B;
  } SEL1;

  union {                              /* Select 2 register */
    vuint32_t R;
    struct {
      vuint32_t A256KSEL:32;           /* 256 KB Block Select. */
    } B;
  } SEL2;

  union {                              /* Select 3 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t A256KSEL:16;           /* 256 KB Block Select. */
    } B;
  } SEL3;

  uint8_t C55FMC_reserved3[8];
  union {                              /* Address register */
    vuint32_t R;
    struct {
      vuint32_t SAD:1;
      vuint32_t aH:1;
      vuint32_t aM:1;
      vuint32_t aL:1;
      vuint32_t a256k:1;
      vuint32_t a64k:1;
      vuint32_t a32k:1;
      vuint32_t a16k:1;
      vuint32_t ADDR:21;
      vuint32_t  :3;
    } B;
  } ADR;

  union {                              /* UTest 0 register */
    vuint32_t R;
    struct {
      vuint32_t UTE:1;
      vuint32_t SBCE:1;
      vuint32_t  :11;
      vuint32_t CPR:1;
      vuint32_t CPA:1;
      vuint32_t CPE:1;
      vuint32_t  :6;
      vuint32_t NAIBP:1;
      vuint32_t AIBPE:1;
      vuint32_t  :1;
      vuint32_t AISUS:1;
      vuint32_t MRE:1;
      vuint32_t MRV:1;
      vuint32_t  :1;
      vuint32_t AIS:1;
      vuint32_t AIE:1;
      vuint32_t AID:1;
    } B;
  } UT0;

  union {                              /* UMISR register */
    vuint32_t R;
    struct {
      vuint32_t MISR:32;
    } B;
  } UM[9];

  union {                              /* UMISR register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t MISR:1;                /* MISR[288]. */
    } B;
  } UM9;

  union {                              /* Over-Program Protection 0 register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t LOWOPP:14;             /* Low Block Over-Program Protection[13:0]. */
      vuint32_t MIDOPP:16;             /* Mid Block Over-Program Protection[15:0]. */
    } B;
  } OPP0;

  union {                              /* Over-Program Protection 1 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HIGHOPP:16;            /* High Block Over-Program Protection[15:0]. */
    } B;
  } OPP1;

  union {                              /* Over-Program Protection 2 register */
    vuint32_t R;
    struct {
      vuint32_t A256KOPP:32;           /* 256K Block Over-Program Protection[31:0]. */
    } B;
  } OPP2;

  union {                              /* Over-Program Protection 3 register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t A256KOPP:16;           /* 256K Block Over-Program Protection[47:32]. */
    } B;
  } OPP3;

  union {                              /* Test Mode Disable Password Check register */
    vuint32_t R;
    struct {
      vuint32_t PWD:32;                /* Password challenge */
    } B;
  } TMD;
};


/* ============================================================================
   =============================== Module: CMU ================================
   ============================================================================ */

struct CMU_tag {
  union {                              /* CMU Control Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SFM:1;                 /* Start frequency measure. */
      vuint32_t  :13;
      vuint32_t CKSEL1:2;              /* Frequency measure clock selection bit. */
      vuint32_t  :5;
      vuint32_t RCDIV:2;               /* CLKMT0_RMN division factor. */
      vuint32_t CME:1;                 /* CLKMN1 monitor enable. */
    } B;
  } CSR;

  union {                              /* CMU Frequency Display Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t FD:20;                 /* Measured frequency bits. */
    } B;
  } FDR;

  union {                              /* CMU High Frequency Reference Register CLKMN1 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t HFREF:12;              /* High Frequency reference value. */
    } B;
  } HFREFR;

  union {                              /* CMU Low Frequency Reference Register CLKMN1 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t LFREF:12;              /* Low Frequency reference value. */
    } B;
  } LFREFR;

  union {                              /* CMU Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t  :1;
      vuint32_t FHHI:1;                /* CLKMN1 frequency higher than high reference event status. */
      vuint32_t FLLI:1;                /* CLKMN1 frequency less than low reference event status. */
      vuint32_t OLRI:1;                /* Oscillator frequency less than f CLKMT0_RMN * 2RCDIVevent status. */
    } B;
  } ISR;

  uint8_t CMU_reserved0[4];
  union {                              /* CMU Measurement Duration Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t MD:20;                 /* Measurement duration bits */
    } B;
  } MDR;
};


/* ============================================================================
   =============================== Module: CRC ================================
   ============================================================================ */

struct CRC_tag {
  union {                              /* Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t  :18;
      vuint32_t SWAP_BYTEWISE:1;       /* Swap CRC_INP byte-wise */
      vuint32_t SWAP_BITWISE:1;        /* Swap CRC_INP bit-wise */
      vuint32_t POLYG:2;               /* Polynomial selection */
      vuint32_t SWAP:1;                /* Swap selection */
      vuint32_t INV:1;                 /* Inversion selection */
    } B;
  } CFG;

  union {                              /* Input Register */
    vuint32_t R;
    struct {
      vuint32_t INP:32;                /* Input data for the CRC computation */
    } B;
  } INP;

  union {                              /* Current Status Register */
    vuint32_t R;
    struct {
      vuint32_t CSTAT:32;              /* CRC signature status */
    } B;
  } CSTAT;

  union {                              /* Output Register */
    vuint32_t R;
    struct {
      vuint32_t OUTP:32;               /* Final CRC signature */
    } B;
  } OUTP;
};


/* ============================================================================
   =============================== Module: DMAMUX =============================
   ============================================================================ */

struct DMAMUX_tag {
  union {                              /* Channel Configuration register */
    vuint8_t R;
    struct {
      vuint8_t ENBL:1;                 /* DMA Channel Enable */
      vuint8_t TRIG:1;                 /* DMA Channel Trigger Enable */
      vuint8_t SOURCE:6;               /* DMA Channel Source (Slot) */
    } B;
//  } CHCFG[16];   /* new style name, v0.9 and later*/
  } CHCONFIG[16];  /* old style name, v0.8 and earlier */
};


/* ============================================================================
   =============================== Module: DSPI ===============================
   ============================================================================ */

struct DSPI_tag {
  union {                              /* DSPI Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t MSTR:1;
      vuint32_t CONT_SCKE:1;
      vuint32_t DCONF:2;
      vuint32_t FRZ:1;
      vuint32_t MTFE:1;
      vuint32_t PCSSE:1;
      vuint32_t ROOE:1;
      vuint32_t PCSIS7:1;
      vuint32_t PCSIS6:1;
      vuint32_t PCSIS5:1;
      vuint32_t PCSIS4:1;
      vuint32_t PCSIS3:1;
      vuint32_t PCSIS2:1;
      vuint32_t PCSIS1:1;
      vuint32_t PCSIS0:1;
      vuint32_t DOZE:1;
      vuint32_t MDIS:1;
      vuint32_t DIS_TXF:1;
      vuint32_t DIS_RXF:1;
      vuint32_t CLR_TXF:1;
      vuint32_t CLR_RXF:1;
      vuint32_t SMPL_PT:2;
      vuint32_t  :4;
      vuint32_t XSPI:1;
      vuint32_t FCPCS:1;
      vuint32_t PES:1;
      vuint32_t HALT:1;
    } B;
  } MCR;

  uint8_t DSPI_reserved0[4];
  union {                              /* DSPI Transfer Count Register */
    vuint32_t R;
    struct {
      vuint32_t SPI_TCNT:16;
      vuint32_t  :16;
    } B;
  } TCR;

  union {
    union {                            /* DSPI Clock and Transfer Attributes Register (In Master Mode) */
      vuint32_t R;
      struct {
        vuint32_t DBR:1;
        vuint32_t FMSZ:4;
        vuint32_t CPOL:1;
        vuint32_t CPHA:1;
        vuint32_t LSBFE:1;
        vuint32_t PCSSCK:2;
        vuint32_t PASC:2;
        vuint32_t PDT:2;
        vuint32_t PBR:2;
        vuint32_t CSSCK:4;
        vuint32_t ASC:4;
        vuint32_t DT:4;
        vuint32_t BR:4;
      } B;
    } CTAR[8];
    union {                            /* DSPI Clock and Transfer Attributes Register (In Slave Mode) */
      vuint32_t R;
      struct {
        vuint32_t FMSZ:5;
        vuint32_t CPOL:1;
        vuint32_t CPHA:1;
        vuint32_t PE:1;
        vuint32_t PP:1;
        vuint32_t FMSZ5:1;
        vuint32_t  :22;
      } B;
    } CTAR_SLAVE[2];
  };

  union {                              /* DSPI Status Register */
    vuint32_t R;
    struct {
      vuint32_t TCF:1;
      vuint32_t TXRXS:1;
      vuint32_t SPITCF:1;
      vuint32_t EOQF:1;
      vuint32_t TFUF:1;
      vuint32_t DSITCF:1;
      vuint32_t TFFF:1;
      vuint32_t BSYF:1;
      vuint32_t CMDTCF:1;
      vuint32_t DPEF:1;
      vuint32_t SPEF:1;
      vuint32_t DDIF:1;
      vuint32_t RFOF:1;
      vuint32_t TFIWF:1;
      vuint32_t RFDF:1;
      vuint32_t CMDFFF:1;
      vuint32_t TXCTR:4;
      vuint32_t TXNXTPTR:4;
      vuint32_t RXCTR:4;
      vuint32_t POPNXTPTR:4;
    } B;
  } SR;

  union {                              /* DSPI DMA/Interrupt Request Select and Enable Register */
    vuint32_t R;
    struct {
      vuint32_t TCF_RE:1;
      vuint32_t CMDFFF_RE:1;
      vuint32_t SPITCF_RE:1;
      vuint32_t EOQF_RE:1;
      vuint32_t TFUF_RE:1;
      vuint32_t DSITCF_RE:1;
      vuint32_t TFFF_RE:1;
      vuint32_t TFFF_DIRS:1;
      vuint32_t CMDTCF_RE:1;
      vuint32_t DPEF_RE:1;
      vuint32_t SPEF_RE:1;
      vuint32_t DDIF_RE:1;
      vuint32_t RFOF_RE:1;
      vuint32_t TFIWF_RE:1;
      vuint32_t RFDF_RE:1;
      vuint32_t RFDF_DIRS:1;
      vuint32_t CMDFFF_DIRS:1;
      vuint32_t DDIF_DIRS:1;
      vuint32_t  :14;
    } B;
  } RSER;

  union {
    union {                            /* DSPI PUSH FIFO Register In Master Mode */
      vuint32_t R;
      struct {
        vuint32_t CONT:1;
        vuint32_t CTAS:3;
        vuint32_t EOQ:1;
        vuint32_t CTCNT:1;
        vuint32_t PE_MASC:1;
        vuint32_t PP_MCSC:1;
        vuint32_t PCS:8;
        vuint32_t TXDATA:16;
      } B;
    } PUSHR;
    union {                            /* DSPI PUSH FIFO Register In Slave Mode */
      vuint32_t R;
      struct {
        vuint32_t  :16;
        vuint32_t TXDATA:16;
      } B;
    } PUSHR_SLAVE;
  };

  union {                              /* DSPI POP FIFO Register */
    vuint32_t R;
    struct {
      vuint32_t RXDATA:32;
    } B;
  } POPR;

  union {                              /* DSPI Transmit FIFO Registers */
    vuint32_t R;
    struct {
      vuint32_t TXCMD_TXDATA:16;
      vuint32_t TXDATA:16;
    } B;
  } TXFR[4];

  uint8_t DSPI_reserved1[48];
  union {                              /* DSPI Receive FIFO Registers */
    vuint32_t R;
    struct {
      vuint32_t RXDATA:32;
    } B;
  } RXFR[4];

  uint8_t DSPI_reserved2[48];
  union {                              /* DSPI DSI Configuration Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t FMSZ4:1;
      vuint32_t  :6;
      vuint32_t FMSZ5:1;
      vuint32_t  :1;
      vuint32_t ITSB:1;
      vuint32_t TSBC:1;
      vuint32_t TXSS:1;
      vuint32_t TPOL:1;
      vuint32_t  :1;
      vuint32_t CID:1;
      vuint32_t DCONT:1;
      vuint32_t DSICTAS:3;
      vuint32_t DMS:1;
      vuint32_t PES:1;
      vuint32_t PE:1;
      vuint32_t PP:1;
      vuint32_t DPCSx:8;
    } B;
  } DSICR0;

  union {                              /* DSPI DSI Serialization Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t SER_DATA:32;
    } B;
  } SDR0;

  union {                              /* DSPI DSI Alternate Serialization Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t ASER_DATA:32;
    } B;
  } ASDR0;

  union {                              /* DSPI DSI Transmit Comparison Register 0 */
    vuint32_t R;
    struct {
      vuint32_t COMP_DATA:32;
    } B;
  } COMPR0;

  union {                              /* DSPI DSI Deserialization Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t DESER_DATA:32;
    } B;
  } DDR0;

  union {                              /* DSPI DSI Configuration Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t TSBCNT:6;
      vuint32_t  :5;
      vuint32_t DSI64E:1;
      vuint32_t DSE1:1;
      vuint32_t DSE0:1;
      vuint32_t TRGPRD:8;
      vuint32_t DPCS1_x:8;
    } B;
  } DSICR1;

  union {                              /* DSPI DSI Serialization Source Select Register 0 */
    vuint32_t R;
    struct {
      vuint32_t SS:32;
    } B;
  } SSR0;

  union {                              /* DSPI DSI Parallel Input Select Register 0 */
    vuint32_t R;
    struct {
      vuint32_t IPS7:4;
      vuint32_t IPS6:4;
      vuint32_t IPS5:4;
      vuint32_t IPS4:4;
      vuint32_t IPS3:4;
      vuint32_t IPS2:4;
      vuint32_t IPS1:4;
      vuint32_t IPS0:4;
    } B;
  } PISR0;

  union {                              /* DSPI DSI Parallel Input Select Register 1 */
    vuint32_t R;
    struct {
      vuint32_t IPS15:4;
      vuint32_t IPS14:4;
      vuint32_t IPS13:4;
      vuint32_t IPS12:4;
      vuint32_t IPS11:4;
      vuint32_t IPS10:4;
      vuint32_t IPS9:4;
      vuint32_t IPS8:4;
    } B;
  } PISR1;

  union {                              /* DSPI DSI Parallel Input Select Register 2 */
    vuint32_t R;
    struct {
      vuint32_t IPS23:4;
      vuint32_t IPS22:4;
      vuint32_t IPS21:4;
      vuint32_t IPS20:4;
      vuint32_t IPS19:4;
      vuint32_t IPS18:4;
      vuint32_t IPS17:4;
      vuint32_t IPS16:4;
    } B;
  } PISR2;

  union {                              /* DSPI DSI Parallel Input Select Register 3 */
    vuint32_t R;
    struct {
      vuint32_t IPS31:4;
      vuint32_t IPS30:4;
      vuint32_t IPS29:4;
      vuint32_t IPS28:4;
      vuint32_t IPS27:4;
      vuint32_t IPS26:4;
      vuint32_t IPS25:4;
      vuint32_t IPS24:4;
    } B;
  } PISR3;

  union {                              /* DSPI DSI Deserialized Data Interrupt Mask Register 0 */
    vuint32_t R;
    struct {
      vuint32_t MASK:32;
    } B;
  } DIMR0;

  union {                              /* DSPI DSI Deserialized Data Polarity Interrupt Register 0 */
    vuint32_t R;
    struct {
      vuint32_t DP:32;
    } B;
  } DPIR0;

  union {                              /* DSPI DSI Serialization Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t SER_DATA:32;
    } B;
  } SDR1;

  union {                              /* DSPI DSI Alternate Serialization Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t ASER_DATA:32;
    } B;
  } ASDR1;

  union {                              /* DSPI DSI Transmit Comparison Register 1 */
    vuint32_t R;
    struct {
      vuint32_t COMP_DATA:32;
    } B;
  } COMPR1;

  union {                              /* DSPI DSI Deserialization Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t DESER_DATA:32;
    } B;
  } DDR1;

  union {                              /* DSPI DSI Serialization Source Select Register 1 */
    vuint32_t R;
    struct {
      vuint32_t SS:32;
    } B;
  } SSR1;

  union {                              /* DSPI DSI Parallel Input Select Register 4 */
    vuint32_t R;
    struct {
      vuint32_t IPS39:4;
      vuint32_t IPS38:4;
      vuint32_t IPS37:4;
      vuint32_t IPS36:4;
      vuint32_t IPS35:4;
      vuint32_t IPS34:4;
      vuint32_t IPS33:4;
      vuint32_t IPS32:4;
    } B;
  } PISR4;

  union {                              /* DSPI DSI Parallel Input Select Register 5 */
    vuint32_t R;
    struct {
      vuint32_t IPS47:4;
      vuint32_t IPS46:4;
      vuint32_t IPS45:4;
      vuint32_t IPS44:4;
      vuint32_t IPS43:4;
      vuint32_t IPS42:4;
      vuint32_t IPS41:4;
      vuint32_t IPS40:4;
    } B;
  } PISR5;

  union {                              /* DSPI DSI Parallel Input Select Register 6 */
    vuint32_t R;
    struct {
      vuint32_t IPS55:4;
      vuint32_t IPS54:4;
      vuint32_t IPS53:4;
      vuint32_t IPS52:4;
      vuint32_t IPS51:4;
      vuint32_t IPS50:4;
      vuint32_t IPS49:4;
      vuint32_t IPS48:4;
    } B;
  } PISR6;

  union {                              /* DSPI DSI Parallel Input Select Register 7 */
    vuint32_t R;
    struct {
      vuint32_t IPS63:4;
      vuint32_t IPS62:4;
      vuint32_t IPS61:4;
      vuint32_t IPS60:4;
      vuint32_t IPS59:4;
      vuint32_t IPS58:4;
      vuint32_t IPS57:4;
      vuint32_t IPS56:4;
    } B;
  } PISR7;

  union {                              /* DSPI DSI Deserialized Data Interrupt Mask Register 1 */
    vuint32_t R;
    struct {
      vuint32_t MASK:32;
    } B;
  } DIMR1;

  union {                              /* DSPI DSI Deserialized Data Polarity Interrupt Register 1 */
    vuint32_t R;
    struct {
      vuint32_t DP:32;
    } B;
  } DPIR1;

  union {                              /* DSPI Clock and Transfer Attributes Register Extended */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t FMSZE:1;
      vuint32_t  :5;
      vuint32_t DTCP:11;
    } B;
  } CTARE[8];

  union {                              /* DSPI Status Register Extended */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t CMDCTR:4;
      vuint32_t CMDNXTPTR:4;
    } B;
  } SREX;
};


/* ============================================================================
   =============================== Module: DTS ================================
   ============================================================================ */

struct DTS_tag {
  union {                              /* Output Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t DTS_EN_B:1;
      vuint32_t DTS_EN:1;
    } B;
  } ENABLE;

  union {                              /* Startup Register */
    vuint32_t R;
    struct {
      vuint32_t AD:32;
    } B;
  } STARTUP;

  union {                              /* Semaphore Register */
    vuint32_t R;
    struct {
      vuint32_t ST:32;
    } B;
  } SEMAPHORE;

  union {                              /* Semaphore Extension */
    vuint32_t R;
    struct {
      vuint32_t ST_B:32;
    } B;
  } SEMAPHORE_B;
};
 
// >>>>> v1.0_issue:  Manually added DWPU <<<<< 

/* ============================================================================
   =============================== Module: DWPU ===============================
   ============================================================================ */

struct DWPU_tag {
  union {
    vuint32_t R;
      struct {
        vuint32_t  :4;					 
        vuint32_t BAL:12;					 /* Block Access Length. Should not cross region boundary. Valid only when BAE = 1 */
        vuint32_t  :5;					 
        vuint32_t EXC:1;					 /* Excess Tag Ram access by IPS */
        vuint32_t PROG:1;					 /* IPS access to Tag Ram in progress */
        vuint32_t INV:1;					 /* Invalid IPS access */
        vuint32_t  :1;					 
        vuint32_t DSM:3;					 /* Data Size Mode */
        vuint32_t  :1;					 
        vuint32_t BAE:1;					 /* Block Access Enable. */
        vuint32_t CMD:2;					 
    } B;
  } TRC_CTRL;

  union {
    vuint32_t R;
      struct {
        vuint32_t ADDR:29;					 
        vuint32_t  :3;					 
    } B;
  } TRC_ADR;

  union {
    vuint32_t R;
      struct {
        vuint32_t DATA:32;					 
    } B;
  } TRC_DATA;

};

/* ============================================================================
   =============================== Module: EBI ================================
   ============================================================================ */

struct EBI_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ACGE:1;
      vuint32_t  :8;
      vuint32_t MDIS:1;
      vuint32_t  :3;
      vuint32_t D16_31:1;
      vuint32_t  :1;
      vuint32_t DBM:1;
    } B;
  } MCR;

  uint8_t EBI_reserved0[12];
  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t  :1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR0;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR0;

  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t  :1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR1;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR1;

  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t  :1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR2;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR2;

  union {                              /* Base Register Bank */
    vuint32_t R;
    struct {
      vuint32_t BA:17;
      vuint32_t  :2;
      vuint32_t LWRN:1;
      vuint32_t PS:1;
      vuint32_t EOE:2;
      vuint32_t SBL:1;
      vuint32_t AD_MUX:1;
      vuint32_t BL:1;
      vuint32_t WEBS:1;
      vuint32_t  :1;
      vuint32_t GCSN:1;
      vuint32_t  :1;
      vuint32_t BI:1;
      vuint32_t V:1;
    } B;
  } BR3;

  union {                              /* Option Register Bank */
    vuint32_t R;
    struct {
      vuint32_t AM:17;
      vuint32_t  :2;
      vuint32_t APS:1;                 /* Address by Port Size */
      vuint32_t  :1;
      vuint32_t AWE:1;                 /* Address / Write Enable Select */
      vuint32_t  :2;
      vuint32_t SCY:4;
      vuint32_t  :1;
      vuint32_t BSCY:2;
      vuint32_t  :1;
    } B;
  } OR3;
};


/* ============================================================================
   =============================== Module: FCCU ===============================
   ============================================================================ */

struct FCCU_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t FILTER_BYPASS:1;
      vuint32_t FILTER_WIDTH:2;
      vuint32_t  :19;
      vuint32_t DEBUG:1;
      vuint32_t  :1;
      vuint32_t OPS:2;
      vuint32_t  :1;
      vuint32_t OPR:5;
    } B;
  } CTRL;

  union {                              /* CTRL Key Register */
    vuint32_t R;
    struct {
      vuint32_t CTRLK:32;
    } B;
  } CTRLK;

  union {                              /* Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t FCCU_SET_AFTER_RESET:1;
      vuint32_t FCCU_SET_CLEAR:2;
      vuint32_t  :2;
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t OD:1;
      vuint32_t  :1;
      vuint32_t SM:1;
      vuint32_t PS:1;
      vuint32_t FOM:3;
      vuint32_t  :6;
    } B;
  } CFG;

  uint8_t FCCU_reserved0[16];
  union {                              /* RF Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t RFC31:1;
      vuint32_t RFC30:1;
      vuint32_t RFC29:1;
      vuint32_t RFC28:1;
      vuint32_t RFC27:1;
      vuint32_t RFC26:1;
      vuint32_t RFC25:1;
      vuint32_t RFC24:1;
      vuint32_t RFC23:1;
      vuint32_t RFC22:1;
      vuint32_t RFC21:1;
      vuint32_t RFC20:1;
      vuint32_t RFC19:1;
      vuint32_t RFC18:1;
      vuint32_t RFC17:1;
      vuint32_t RFC16:1;
      vuint32_t RFC15:1;
      vuint32_t RFC14:1;
      vuint32_t RFC13:1;
      vuint32_t RFC12:1;
      vuint32_t RFC11:1;
      vuint32_t RFC10:1;
      vuint32_t RFC9:1;
      vuint32_t RFC8:1;
      vuint32_t RFC7:1;
      vuint32_t RFC6:1;
      vuint32_t RFC5:1;
      vuint32_t RFC4:1;
      vuint32_t RFC3:1;
      vuint32_t RFC2:1;
      vuint32_t RFC1:1;
      vuint32_t RFC0:1;
    } B;
  } NCF_CFG[4];

  uint8_t FCCU_reserved1[32];
  union {                              /* RFS Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t RFSC31:1;
      vuint32_t RFSC30:1;
      vuint32_t RFSC29:1;
      vuint32_t RFSC28:1;
      vuint32_t RFSC27:1;
      vuint32_t RFSC26:1;
      vuint32_t RFSC25:1;
      vuint32_t RFSC24:1;
      vuint32_t RFSC23:1;
      vuint32_t RFSC22:1;
      vuint32_t RFSC21:1;
      vuint32_t RFSC20:1;
      vuint32_t RFSC19:1;
      vuint32_t RFSC18:1;
      vuint32_t RFSC17:1;
      vuint32_t RFSC16:1;
      vuint32_t RFSC15:1;
      vuint32_t RFSC14:1;
      vuint32_t RFSC13:1;
      vuint32_t RFSC12:1;
      vuint32_t RFSC11:1;
      vuint32_t RFSC10:1;
      vuint32_t RFSC9:1;
      vuint32_t RFSC8:1;
      vuint32_t RFSC7:1;
      vuint32_t RFSC6:1;
      vuint32_t RFSC5:1;
      vuint32_t RFSC4:1;
      vuint32_t RFSC3:1;
      vuint32_t RFSC2:1;
      vuint32_t RFSC1:1;
      vuint32_t RFSC0:1;
    } B;
  } RFS_CFG[8];

  uint8_t FCCU_reserved2[20];
  union {                              /* UF Status Register */
    vuint32_t R;
    struct {
      vuint32_t RFS31:1;
      vuint32_t RFS30:1;
      vuint32_t RFS29:1;
      vuint32_t RFS28:1;
      vuint32_t RFS27:1;
      vuint32_t RFS26:1;
      vuint32_t RFS25:1;
      vuint32_t RFS24:1;
      vuint32_t RFS23:1;
      vuint32_t RFS22:1;
      vuint32_t RFS21:1;
      vuint32_t RFS20:1;
      vuint32_t RFS19:1;
      vuint32_t RFS18:1;
      vuint32_t RFS17:1;
      vuint32_t RFS16:1;
      vuint32_t RFS15:1;
      vuint32_t RFS14:1;
      vuint32_t RFS13:1;
      vuint32_t RFS12:1;
      vuint32_t RFS11:1;
      vuint32_t RFS10:1;
      vuint32_t RFS9:1;
      vuint32_t RFS8:1;
      vuint32_t RFS7:1;
      vuint32_t RFS6:1;
      vuint32_t RFS5:1;
      vuint32_t RFS4:1;
      vuint32_t RFS3:1;
      vuint32_t RFS2:1;
      vuint32_t RFS1:1;
      vuint32_t RFS0:1;
    } B;
  } RF_S[4];

  union {                              /* RF Key Register */
    vuint32_t R;
    struct {
      vuint32_t RFK:32;
    } B;
  } RFK;

  union {                              /* RF Enable Register */
    vuint32_t R;
    struct {
      vuint32_t RFE31:1;
      vuint32_t RFE30:1;
      vuint32_t RFE29:1;
      vuint32_t RFE28:1;
      vuint32_t RFE27:1;
      vuint32_t RFE26:1;
      vuint32_t RFE25:1;
      vuint32_t RFE24:1;
      vuint32_t RFE23:1;
      vuint32_t RFE22:1;
      vuint32_t RFE21:1;
      vuint32_t RFE20:1;
      vuint32_t RFE19:1;
      vuint32_t RFE18:1;
      vuint32_t RFE17:1;
      vuint32_t RFE16:1;
      vuint32_t RFE15:1;
      vuint32_t RFE14:1;
      vuint32_t RFE13:1;
      vuint32_t RFE12:1;
      vuint32_t RFE11:1;
      vuint32_t RFE10:1;
      vuint32_t RFE9:1;
      vuint32_t RFE8:1;
      vuint32_t RFE7:1;
      vuint32_t RFE6:1;
      vuint32_t RFE5:1;
      vuint32_t RFE4:1;
      vuint32_t RFE3:1;
      vuint32_t RFE2:1;
      vuint32_t RFE1:1;
      vuint32_t RFE0:1;
    } B;
  } NCF_E[4];

  union {                              /* RF Time-out Enable Register */
    vuint32_t R;
    struct {
      vuint32_t RFTOE31:1;
      vuint32_t RFTOE30:1;
      vuint32_t RFTOE29:1;
      vuint32_t RFTOE28:1;
      vuint32_t RFTOE27:1;
      vuint32_t RFTOE26:1;
      vuint32_t RFTOE25:1;
      vuint32_t RFTOE24:1;
      vuint32_t RFTOE23:1;
      vuint32_t RFTOE22:1;
      vuint32_t RFTOE21:1;
      vuint32_t RFTOE20:1;
      vuint32_t RFTOE19:1;
      vuint32_t RFTOE18:1;
      vuint32_t RFTOE17:1;
      vuint32_t RFTOE16:1;
      vuint32_t RFTOE15:1;
      vuint32_t RFTOE14:1;
      vuint32_t RFTOE13:1;
      vuint32_t RFTOE12:1;
      vuint32_t RFTOE11:1;
      vuint32_t RFTOE10:1;
      vuint32_t RFTOE9:1;
      vuint32_t RFTOE8:1;
      vuint32_t RFTOE7:1;
      vuint32_t RFTOE6:1;
      vuint32_t RFTOE5:1;
      vuint32_t RFTOE4:1;
      vuint32_t RFTOE3:1;
      vuint32_t RFTOE2:1;
      vuint32_t RFTOE1:1;
      vuint32_t RFTOE0:1;
    } B;
  } NCF_TOE[4];

  union {                              /* RF Time-out Register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;
    } B;
  } RF_TO;

  union {                              /* CFG Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TO:3;
    } B;
  } CFG_TO;

  union {                              /* IO Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t EIN1:1;
      vuint32_t EIN0:1;
      vuint32_t  :2;
      vuint32_t EOUT1:1;
      vuint32_t EOUT0:1;
    } B;
  } EINOUT;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t PhysicErrorPin:2;
      vuint32_t ESTAT:1;
      vuint32_t STATUS:3;
    } B;
  } STAT;

  union {                              /* NA Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t NAFS:8;
    } B;
  } N2AF_STATUS;

  union {                              /* AF Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t AF_SRC:2;
      vuint32_t AFFS:8;
    } B;
  } A2FF_STATUS;

  union {                              /* NF Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t NF_SRC:2;
      vuint32_t NFFS:8;
    } B;
  } N2FF_STATUS;

  union {                              /* FA Freeze Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t FAFS:9;
    } B;
  } F2A_STATUS;

  uint8_t FCCU_reserved3[8];
  union {                              /* RF Fake Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FRFC:7;
    } B;
  } RFF;

  union {                              /* IRQ Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t NMI_STAT:1;
      vuint32_t ALRM_STAT:1;
      vuint32_t CFG_TO_STAT:1;
    } B;
  } IRQ_STAT;

  union {                              /* IRQ Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t CFG_TO_IEN:1;
    } B;
  } IRQ_EN;

  union {                              /* XTMR Register */
    vuint32_t R;
    struct {
      vuint32_t XTMR:32;
    } B;
  } XTMR;

  union {                              /* MCS Register */
    vuint32_t R;
    struct {
      vuint32_t VL3:1;
      vuint32_t FS3:1;
      vuint32_t  :2;
      vuint32_t MCS3:4;
      vuint32_t VL2:1;
      vuint32_t FS2:1;
      vuint32_t  :2;
      vuint32_t MCS2:4;
      vuint32_t VL1:1;
      vuint32_t FS1:1;
      vuint32_t  :2;
      vuint32_t MCS1:4;
      vuint32_t VL0:1;
      vuint32_t FS0:1;
      vuint32_t  :2;
      vuint32_t MCS0:4;
    } B;
  } MCS;

  union {                              /* Transient Lock Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t TRANSKEY:9;
    } B;
  } TRANS_LOCK;

  union {                              /* Permanent Lock Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t PERMNTKEY:9;
    } B;
  } PERMNT_LOCK;

  union {                              /* Delta T Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t  :14;
      vuint32_t  :2;
      vuint32_t DELTA_T:14;
    } B;
  } DELTA_T;

  union {                              /* IRQ Alarm Enable Register */
    vuint32_t R;
    struct {
      vuint32_t IRQEN31:1;
      vuint32_t IRQEN30:1;
      vuint32_t IRQEN29:1;
      vuint32_t IRQEN28:1;
      vuint32_t IRQEN27:1;
      vuint32_t IRQEN26:1;
      vuint32_t IRQEN25:1;
      vuint32_t IRQEN24:1;
      vuint32_t IRQEN23:1;
      vuint32_t IRQEN22:1;
      vuint32_t IRQEN21:1;
      vuint32_t IRQEN20:1;
      vuint32_t IRQEN19:1;
      vuint32_t IRQEN18:1;
      vuint32_t IRQEN17:1;
      vuint32_t IRQEN16:1;
      vuint32_t IRQEN15:1;
      vuint32_t IRQEN14:1;
      vuint32_t IRQEN13:1;
      vuint32_t IRQEN12:1;
      vuint32_t IRQEN11:1;
      vuint32_t IRQEN10:1;
      vuint32_t IRQEN9:1;
      vuint32_t IRQEN8:1;
      vuint32_t IRQEN7:1;
      vuint32_t IRQEN6:1;
      vuint32_t IRQEN5:1;
      vuint32_t IRQEN4:1;
      vuint32_t IRQEN3:1;
      vuint32_t IRQEN2:1;
      vuint32_t IRQEN1:1;
      vuint32_t IRQEN0:1;
    } B;
  } IRQ_ALARM_EN[4];

  union {                              /* NMI Enable Register */
    vuint32_t R;
    struct {
      vuint32_t NMIEN31:1;
      vuint32_t NMIEN30:1;
      vuint32_t NMIEN29:1;
      vuint32_t NMIEN28:1;
      vuint32_t NMIEN27:1;
      vuint32_t NMIEN26:1;
      vuint32_t NMIEN25:1;
      vuint32_t NMIEN24:1;
      vuint32_t NMIEN23:1;
      vuint32_t NMIEN22:1;
      vuint32_t NMIEN21:1;
      vuint32_t NMIEN20:1;
      vuint32_t NMIEN19:1;
      vuint32_t NMIEN18:1;
      vuint32_t NMIEN17:1;
      vuint32_t NMIEN16:1;
      vuint32_t NMIEN15:1;
      vuint32_t NMIEN14:1;
      vuint32_t NMIEN13:1;
      vuint32_t NMIEN12:1;
      vuint32_t NMIEN11:1;
      vuint32_t NMIEN10:1;
      vuint32_t NMIEN9:1;
      vuint32_t NMIEN8:1;
      vuint32_t NMIEN7:1;
      vuint32_t NMIEN6:1;
      vuint32_t NMIEN5:1;
      vuint32_t NMIEN4:1;
      vuint32_t NMIEN3:1;
      vuint32_t NMIEN2:1;
      vuint32_t NMIEN1:1;
      vuint32_t NMIEN0:1;
    } B;
  } NMI_EN[4];

  union {                              /* EOUT Signaling Enable Register */
    vuint32_t R;
    struct {
      vuint32_t EOUTEN31:1;
      vuint32_t EOUTEN30:1;
      vuint32_t EOUTEN29:1;
      vuint32_t EOUTEN28:1;
      vuint32_t EOUTEN27:1;
      vuint32_t EOUTEN26:1;
      vuint32_t EOUTEN25:1;
      vuint32_t EOUTEN24:1;
      vuint32_t EOUTEN23:1;
      vuint32_t EOUTEN22:1;
      vuint32_t EOUTEN21:1;
      vuint32_t EOUTEN20:1;
      vuint32_t EOUTEN19:1;
      vuint32_t EOUTEN18:1;
      vuint32_t EOUTEN17:1;
      vuint32_t EOUTEN16:1;
      vuint32_t EOUTEN15:1;
      vuint32_t EOUTEN14:1;
      vuint32_t EOUTEN13:1;
      vuint32_t EOUTEN12:1;
      vuint32_t EOUTEN11:1;
      vuint32_t EOUTEN10:1;
      vuint32_t EOUTEN9:1;
      vuint32_t EOUTEN8:1;
      vuint32_t EOUTEN7:1;
      vuint32_t EOUTEN6:1;
      vuint32_t EOUTEN5:1;
      vuint32_t EOUTEN4:1;
      vuint32_t EOUTEN3:1;
      vuint32_t EOUTEN2:1;
      vuint32_t EOUTEN1:1;
      vuint32_t EOUTEN0:1;
    } B;
  } EOUT_SIG_EN[4];
};


/* ============================================================================
   =============================== Module: FEC ================================
   ============================================================================ */

struct FEC_tag {
  uint8_t FEC_reserved0[4];
  union {                              /* Interrupt Event Register */
    vuint32_t R;
    struct {
      vuint32_t HBERR:1;
      vuint32_t BABR:1;
      vuint32_t BABT:1;
      vuint32_t GRA:1;
      vuint32_t TXF:1;
      vuint32_t TXB:1;
      vuint32_t RXF:1;
      vuint32_t RXB:1;
      vuint32_t MII:1;
      vuint32_t EBERR:1;
      vuint32_t LC:1;
      vuint32_t RL:1;
      vuint32_t UN:1;
      vuint32_t  :19;
    } B;
  } EIR;

  union {                              /* Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t HBERR:1;
      vuint32_t BABR:1;
      vuint32_t BABT:1;
      vuint32_t GRA:1;
      vuint32_t TXF:1;
      vuint32_t TXB:1;
      vuint32_t RXF:1;
      vuint32_t RXB:1;
      vuint32_t MII:1;
      vuint32_t EBERR:1;
      vuint32_t LC:1;
      vuint32_t RL:1;
      vuint32_t UN:1;
      vuint32_t  :19;
    } B;
  } EIMR;

  uint8_t FEC_reserved1[4];
  union {                              /* Receive Descriptor Active Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t RDAR:1;
      vuint32_t  :24;
    } B;
  } RDAR;

  union {                              /* Transmit Descriptor Active Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t TDAR:1;
      vuint32_t  :24;
    } B;
  } TDAR;

  uint8_t FEC_reserved2[12];
  union {                              /* Ethernet Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :23;
      vuint32_t  :1;
      vuint32_t ETHER_EN:1;
      vuint32_t RESET:1;
    } B;
  } ECR;

  uint8_t FEC_reserved3[24];
  union {                              /* MII Management Frame Register */
    vuint32_t R;
    struct {
      vuint32_t ST:2;
      vuint32_t OP:2;
      vuint32_t PA:5;
      vuint32_t RA:5;
      vuint32_t TA:2;
      vuint32_t DATA:16;
    } B;
  } MMFR;

  union {                              /* MII Speed Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t DIS_PRE:1;
      vuint32_t MII_SPEED:6;
      vuint32_t  :1;
    } B;
  } MSCR;

  uint8_t FEC_reserved4[28];
  union {                              /* MIB Control Register */
    vuint32_t R;
    struct {
      vuint32_t MIB_DIS:1;
      vuint32_t MIB_IDLE:1;
      vuint32_t  :30;
    } B;
  } MIBC;

  uint8_t FEC_reserved5[28];
  union {                              /* Receive Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t MAX_FL:11;
      vuint32_t  :4;
      vuint32_t RMII_ECHO:1;
      vuint32_t RMII_LOOP:1;
      vuint32_t RMII_10T:1;
      vuint32_t RMII_MODE:1;
      vuint32_t  :2;
      vuint32_t FCE:1;
      vuint32_t BC_REJ:1;
      vuint32_t PROM:1;
      vuint32_t MII_MODE:1;
      vuint32_t DRT:1;
      vuint32_t LOOP:1;
    } B;
  } RCR;

  uint8_t FEC_reserved6[60];
  union {                              /* Transmit Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t RFC_PAUSE:1;
      vuint32_t TFC_PAUSE:1;
      vuint32_t FDEN:1;
      vuint32_t HBC:1;
      vuint32_t GTS:1;
    } B;
  } TCR;

  uint8_t FEC_reserved7[28];
  union {                              /* Physical Address Low Register */
    vuint32_t R;
    struct {
      vuint32_t PADDR1:32;
    } B;
  } PALR;

  union {                              /* Physical Address High Register and Type Field */
    vuint32_t R;
    struct {
      vuint32_t PADDR2:16;
      vuint32_t TYPE:16;
    } B;
  } PAUR;

  union {                              /* Opcode/Pause Duration */
    vuint32_t R;
    struct {
      vuint32_t OPCODE:16;
      vuint32_t PAUSE_DUR:16;
    } B;
  } OPD;

  uint8_t FEC_reserved8[40];
  union {                              /* Descriptor Individual Upper Address Register */
    vuint32_t R;
    struct {
      vuint32_t IADDR1:32;
    } B;
  } IAUR;

  union {                              /* Descriptor Individual Lower Address Register */
    vuint32_t R;
    struct {
      vuint32_t IADDR2:32;
    } B;
  } IALR;

  union {                              /* Descriptor Group Upper Address Register */
    vuint32_t R;
    struct {
      vuint32_t GADDR1:32;
    } B;
  } GAUR;

  union {                              /* Descriptor Group Lower Address Register */
    vuint32_t R;
    struct {
      vuint32_t GADDR2:32;
    } B;
  } GALR;

  uint8_t FEC_reserved9[28];
  union {                              /* Transmit FIFO Watermark */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t TFWR:2;
    } B;
  } TFWR;

  uint8_t FEC_reserved10[4];
  union {                              /* FIFO Receive Bound Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t R_BOUND:8;
      vuint32_t  :2;
    } B;
  } FRBR;

  union {                              /* FIFO Receive Start Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t R_FSTART:8;
      vuint32_t  :2;
    } B;
  } FRSR;

  uint8_t FEC_reserved11[44];
  union {                              /* Receive Descriptor Ring Start Register */
    vuint32_t R;
    struct {
      vuint32_t R_DES_START:30;
      vuint32_t  :2;
    } B;
  } ERDSR;

  union {                              /* Transmit Buffer Descriptor Ring Start Register */
    vuint32_t R;
    struct {
      vuint32_t X_DES_START:30;
      vuint32_t  :2;
    } B;
  } ETDSR;

  union {                              /* Receive Buffer Size Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t R_BUF_SIZE:7;
      vuint32_t  :4;
    } B;
  } EMRBR;

  uint8_t FEC_reserved12[116];
  union {                              /* Count of frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_DROP:32;
    } B;
  } RMON_T_DROP;

  union {                              /* RMON Tx packet count */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_PACKETS:32;
    } B;
  } RMON_T_PACKETS;

  union {                              /* RMON Tx broadcast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_BC_PKT:32;
    } B;
  } RMON_T_BC_PKT;

  union {                              /* RMON Tx multicast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_MC_PKT:32;
    } B;
  } RMON_T_MC_PKT;

  union {                              /* RMON Tx packets with CRC/align error */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_CRC_ALIGN:32;
    } B;
  } RMON_T_CRC_ALIGN;

  union {                              /* RMON Tx packets < 64 bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_UNDERSIZE:32;
    } B;
  } RMON_T_UNDERSIZE;

  union {                              /* RMON Tx packets > MAX_FL bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_OVERSIZE:32;
    } B;
  } RMON_T_OVERSIZE;

  union {                              /* RMON Tx packets < 64 bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_FRAG:32;
    } B;
  } RMON_T_FRAG;

  union {                              /* RMON Tx packets > MAX_FL bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_JAB:32;
    } B;
  } RMON_T_JAB;

  union {                              /* RMON Tx collision count */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_COL:32;
    } B;
  } RMON_T_COL;

  union {                              /* RMON Tx 64 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P64:32;
    } B;
  } RMON_T_P64;

  union {                              /* RMON Tx 65 to 127 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P65TO127:32;
    } B;
  } RMON_T_P65TO127;

  union {                              /* RMON Tx 128 to 255 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P128TO255:32;
    } B;
  } RMON_T_P128TO255;

  union {                              /* RMON Tx 256 to 511 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P256TO511:32;
    } B;
  } RMON_T_P256TO511;

  union {                              /* RMON Tx 512 to 1023 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P512TO1023:32;
    } B;
  } RMON_T_P512TO1023;

  union {                              /* RMON Tx 1024 to 2047 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P1024TO2047:32;
    } B;
  } RMON_T_P1024TO2047;

  union {                              /* RMON Tx packets with > 2048 bytes */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_P_GTE2048:32;
    } B;
  } RMON_T_P_GTE2048;

  union {                              /* RMON Tx Octets */
    vuint32_t R;
    struct {
      vuint32_t RMON_T_OCTETS:32;
    } B;
  } RMON_T_OCTETS;

  union {                              /* Count of transmitted frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_DROP:32;
    } B;
  } IEEE_T_DROP;

  union {                              /* Frames transmitted OK */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_FRAME_OK:32;
    } B;
  } IEEE_T_FRAME_OK;

  union {                              /* Frames transmitted with single collision */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_1COL:32;
    } B;
  } IEEE_T_1COL;

  union {                              /* Frames transmitted with multiple collisions */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_MCOL:32;
    } B;
  } IEEE_T_MCOL;

  union {                              /* Frames transmitted after deferral delay */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_DEF:32;
    } B;
  } IEEE_T_DEF;

  union {                              /* Frames transmitted with late collision */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_LCOL:32;
    } B;
  } IEEE_T_LCOL;

  union {                              /* Frames transmitted with excessive collisions */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_EXCOL:32;
    } B;
  } IEEE_T_EXCOL;

  union {                              /* Frames transmitted with Tx FIFO underrun */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_MACERR:32;
    } B;
  } IEEE_T_MACERR;

  union {                              /* Frames transmitted with carrier sense error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_CSERR:32;
    } B;
  } IEEE_T_CSERR;

  union {                              /* Frames transmitted with SQE error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_SQE:32;
    } B;
  } IEEE_T_SQE;

  union {                              /* Flow control pause frames transmitted */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_FDXFC:32;
    } B;
  } IEEE_T_FDXFC;

  union {                              /* Octet count for frames transmitted without error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_T_OCTETS_OK:32;
    } B;
  } IEEE_T_OCTETS_OK;

  uint8_t FEC_reserved13[8];
  union {                              /* Count of received frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_DROP:32;
    } B;
  } RMON_R_DROP;

  union {                              /* RMON Rx packet count */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_PACKETS:32;
    } B;
  } RMON_R_PACKETS;

  union {                              /* RMON Rx broadcast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_BC_PKT:32;
    } B;
  } RMON_R_BC_PKT;

  union {                              /* RMON Rx multicast packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_MC_PKT:32;
    } B;
  } RMON_R_MC_PKT;

  union {                              /* RMON Rx packets with CRC/Align error */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_CRC_ALIGN:32;
    } B;
  } RMON_R_CRC_ALIGN;

  union {                              /* RMON Rx packets < 64 bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_UNDERSIZE:32;
    } B;
  } RMON_R_UNDERSIZE;

  union {                              /* RMON Rx packets > MAX_FL bytes, good CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_OVERSIZE:32;
    } B;
  } RMON_R_OVERSIZE;

  union {                              /* RMON Rx packets < 64 bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_FRAG:32;
    } B;
  } RMON_R_FRAG;

  union {                              /* RMON Rx packets > MAX_FL bytes, bad CRC */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_JAB:32;
    } B;
  } RMON_R_JAB;

  union {                              /* Reserved */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_RESVD_0:32;
    } B;
  } RMON_R_RESVD_0;

  union {                              /* RMON Rx 64 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P64:32;
    } B;
  } RMON_R_P64;

  union {                              /* RMON Rx 65 to 127 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P65TO127:32;
    } B;
  } RMON_R_P65TO127;

  union {                              /* RMON Rx 128 to 255 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P128TO255:32;
    } B;
  } RMON_R_P128TO255;

  union {                              /* RMON Rx 256 to 511 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P256TO511:32;
    } B;
  } RMON_R_P256TO511;

  union {                              /* RMON Rx 512 to 1023 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P512TO1023:32;
    } B;
  } RMON_R_P512TO1023;

  union {                              /* RMON Rx 1024 to 2047 byte packets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P1024TO2047:32;
    } B;
  } RMON_R_P1024TO2047;

  union {                              /* RMON Rx packets with > 2048 bytes */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_P_GTE2048:32;
    } B;
  } RMON_R_P_GTE2048;

  union {                              /* RMON Rx octets */
    vuint32_t R;
    struct {
      vuint32_t RMON_R_OCTETS:32;
    } B;
  } RMON_R_OCTETS;

  union {                              /* Count of received frames not counted correctly */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_DROP:32;
    } B;
  } IEEE_R_DROP;

  union {                              /* Frames received OK */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_FRAME_OK:32;
    } B;
  } IEEE_R_FRAME_OK;

  union {                              /* Frames received with CRC error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_CRC:32;
    } B;
  } IEEE_R_CRC;

  union {                              /* Frames received with alignment error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_ALIGN:32;
    } B;
  } IEEE_R_ALIGN;

  union {                              /* Receive FIFO overflow count */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_MACERR:32;
    } B;
  } IEEE_R_MACERR;

  union {                              /* Flow control pause frames received */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_FDXFC:32;
    } B;
  } IEEE_R_FDXFC;

  union {                              /* Octet count for frames received without error */
    vuint32_t R;
    struct {
      vuint32_t IEEE_R_OCTETS_OK:32;
    } B;
  } IEEE_R_OCTETS_OK;
};


/* ============================================================================
   =============================== Module: FR =================================
   ============================================================================ */

struct FR_tag {
  union {                              /* Module Version Register */
    vuint16_t R;
    struct {
      vuint16_t CHIVER:8;
      vuint16_t PEVER:8;
    } B;
  } MVR;

  union {                              /* Module Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t MEN:1;
      vuint16_t SBFF:1;                /* System Bus Failure Freeze */
      vuint16_t SCM:1;
      vuint16_t CHB:1;
      vuint16_t CHA:1;
      vuint16_t SFFE:1;
      vuint16_t ECCE:1;
      vuint16_t  :1;                   /* Reserved bit, will not be changed. Application must not write any value different from the reset value. */
      vuint16_t FUM:1;
      vuint16_t FAM:1;
      vuint16_t  :1;
      vuint16_t CLKSEL:1;
      vuint16_t BITRATE:3;
      vuint16_t  :1;
    } B;
  } MCR;

  union {                              /* System Memory Base Address High Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:16;               /* System Memory Base Address high. This is the value of the system memory base address for the individual message buffers and sync frame table. This is the value of the system memory base address for the receive FIFO if the FIFO address mode bit FR_MCR[FAM] is set to 1. It is defines as a byte address. */
    } B;
  } SYMBADHR;

  union {                              /* System Memory Base Address Low Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:12;
      vuint16_t  :4;
    } B;
  } SYMBADLR;

  union {                              /* Strobe Signal Control Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :3;
      vuint16_t SEL:4;
      vuint16_t  :3;
      vuint16_t ENB:1;
      vuint16_t  :2;
      vuint16_t STBPSEL:2;
    } B;
  } STBSCR;

  uint8_t FR_reserved0[2];
  union {                              /* Message Buffer Data Size Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t MBSEG2DS:7;
      vuint16_t  :1;
      vuint16_t MBSEG1DS:7;
    } B;
  } MBDSR;

  union {                              /* Message Buffer Segment Size and Utilization Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t LAST_MB_SEG1:7;
      vuint16_t  :1;
      vuint16_t LAST_MB_UTIL:7;
    } B;
  } MBSSUTR;

  union {                              /* PE DRAM Access Register */
    vuint16_t R;
    struct {
      vuint16_t INST:4;
      vuint16_t ADDR:11;
      vuint16_t DAD:1;
    } B;
  } PEDRAR;

  union {                              /* PE DRAM Data Register */
    vuint16_t R;
    struct {
      vuint16_t DATA:16;
    } B;
  } PEDRDR;

  union {                              /* Protocol Operation Control Register */
    vuint16_t R;
    struct {
      vuint16_t WME:1;
      vuint16_t  :3;
      vuint16_t EOC_AP:2;
      vuint16_t ERC_AP:2;
      vuint16_t BSY_WMC:1;
      vuint16_t  :3;
      vuint16_t POCCMD:4;
    } B;
  } POCR;

  union {                              /* Global Interrupt Flag and Enable Register */
    vuint16_t R;
    struct {
      vuint16_t MIF:1;
      vuint16_t PRIF:1;
      vuint16_t CHIF:1;
      vuint16_t WUPIF:1;
      vuint16_t FAFBIF:1;
      vuint16_t FAFAIF:1;
      vuint16_t RBIF:1;
      vuint16_t TBIF:1;
      vuint16_t MIE:1;
      vuint16_t PRIE:1;
      vuint16_t CHIE:1;
      vuint16_t WUPIE:1;
      vuint16_t FAFBIE:1;
      vuint16_t FAFAIE:1;
      vuint16_t RBIE:1;
      vuint16_t TBIE:1;
    } B;
  } GIFER;

  union {                              /* Protocol Interrupt Flag Register 0 */
    vuint16_t R;
    struct {
      vuint16_t FATL_IF:1;
      vuint16_t INTL_IF:1;
      vuint16_t ILCF_IF:1;
      vuint16_t CSA_IF:1;
      vuint16_t MRC_IF:1;
      vuint16_t MOC_IF:1;
      vuint16_t CCL_IF:1;
      vuint16_t MXS_IF:1;
      vuint16_t MTX_IF:1;
      vuint16_t LTXB_IF:1;
      vuint16_t LTXA_IF:1;
      vuint16_t TBVB_IF:1;
      vuint16_t TBVA_IF:1;
      vuint16_t TI2_IF:1;
      vuint16_t TI1_IF:1;
      vuint16_t CYS_IF:1;
    } B;
  } PIFR0;

  union {                              /* Protocol Interrupt Flag Register 1 */
    vuint16_t R;
    struct {
      vuint16_t EMC_IF:1;
      vuint16_t IPC_IF:1;
      vuint16_t PECF_IF:1;
      vuint16_t PSC_IF:1;
      vuint16_t SSI3_IF:1;
      vuint16_t SSI2_IF:1;
      vuint16_t SSI1_IF:1;
      vuint16_t SSI0_IF:1;
      vuint16_t  :2;
      vuint16_t EVT_IF:1;
      vuint16_t ODT_IF:1;
      vuint16_t  :4;
    } B;
  } PIFR1;

  union {                              /* Protocol Interrupt Enable Register 0 */
    vuint16_t R;
    struct {
      vuint16_t FATL_IE:1;
      vuint16_t INTL_IE:1;
      vuint16_t ILCF_IE:1;
      vuint16_t CSA_IE:1;
      vuint16_t MRC_IE:1;
      vuint16_t MOC_IE:1;
      vuint16_t CCL_IE:1;
      vuint16_t MXS_IE:1;
      vuint16_t MTX_IE:1;
      vuint16_t LTXB_IE:1;
      vuint16_t LTXA_IE:1;
      vuint16_t TBVB_IE:1;
      vuint16_t TBVA_IE:1;
      vuint16_t TI2_IE:1;
      vuint16_t TI1_IE:1;
      vuint16_t CYS_IE:1;
    } B;
  } PIER0;

  union {                              /* Protocol Interrupt Enable Register 1 */
    vuint16_t R;
    struct {
      vuint16_t EMC_IE:1;
      vuint16_t IPC_IE:1;
      vuint16_t PECF_IE:1;
      vuint16_t PSC_IE:1;
      vuint16_t SSI3_IE:1;
      vuint16_t SSI2_IE:1;
      vuint16_t SSI1_IE:1;
      vuint16_t SSI0_IE:1;
      vuint16_t  :2;
      vuint16_t EVT_IE:1;
      vuint16_t ODT_IE:1;
      vuint16_t  :4;
    } B;
  } PIER1;

  union {                              /* CHI Error Flag Register */
    vuint16_t R;
    struct {
      vuint16_t FRLB_EF:1;
      vuint16_t FRLA_EF:1;
      vuint16_t PCMI_EF:1;
      vuint16_t FOVB_EF:1;
      vuint16_t FOVA_EF:1;
      vuint16_t MBS_EF:1;
      vuint16_t MBU_EF:1;
      vuint16_t LCK_EF:1;
      vuint16_t  :1;
      vuint16_t SBCF_EF:1;
      vuint16_t FID_EF:1;
      vuint16_t DPL_EF:1;
      vuint16_t SPL_EF:1;
      vuint16_t NML_EF:1;
      vuint16_t NMF_EF:1;
      vuint16_t ILSA_EF:1;
    } B;
  } CHIERFR;

  union {                              /* Message Buffer Interrupt Vector Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t TBIVEC:7;
      vuint16_t  :1;
      vuint16_t RBIVEC:7;
    } B;
  } MBIVEC;

  union {                              /* Channel A Status Error Counter Register */
    vuint16_t R;
    struct {
      vuint16_t CHAERSCNT:16;
    } B;
  } CASERCR;

  union {                              /* Channel B Status Error Counter Register */
    vuint16_t R;
    struct {
      vuint16_t CHBERSCNT:16;
    } B;
  } CBSERCR;

  union {                              /* Protocol Status Register 0 */
    vuint16_t R;
    struct {
      vuint16_t ERRMODE:2;
      vuint16_t SLOTMODE:2;
      vuint16_t  :1;
      vuint16_t PROTSTATE:3;
      vuint16_t STARTUPSTATE:4;
      vuint16_t  :1;
      vuint16_t WAKEUPSTATUS:3;
    } B;
  } PSR0;

  union {                              /* Protocol Status Register 1 */
    vuint16_t R;
    struct {
      vuint16_t CSAA:1;
      vuint16_t CSP:1;
      vuint16_t  :1;
      vuint16_t REMCSAT:5;
      vuint16_t CPN:1;
      vuint16_t HHR:1;
      vuint16_t FRZ:1;
      vuint16_t APTAC:5;
    } B;
  } PSR1;

  union {                              /* Protocol Status Register 2 */
    vuint16_t R;
    struct {
      vuint16_t NBVB:1;
      vuint16_t NSEB:1;
      vuint16_t STCB:1;
      vuint16_t SBVB:1;
      vuint16_t SSEB:1;
      vuint16_t MTB:1;
      vuint16_t NBVA:1;
      vuint16_t NSEA:1;
      vuint16_t STCA:1;
      vuint16_t SBVA:1;
      vuint16_t SSEA:1;
      vuint16_t MTA:1;
      vuint16_t CKCORFCNT:4;
    } B;
  } PSR2;

  union {                              /* Protocol Status Register 3 */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t WUB:1;
      vuint16_t ABVB:1;
      vuint16_t AACB:1;
      vuint16_t ACEB:1;
      vuint16_t ASEB:1;
      vuint16_t AVFB:1;
      vuint16_t  :2;
      vuint16_t WUA:1;
      vuint16_t ABVA:1;
      vuint16_t AACA:1;
      vuint16_t ACEA:1;
      vuint16_t ASEA:1;
      vuint16_t AVFA:1;
    } B;
  } PSR3;

  union {                              /* Macrotick Counter Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t MTCT:14;
    } B;
  } MTCTR;

  union {                              /* Cycle Counter Register */
    vuint16_t R;
    struct {
      vuint16_t  :10;
      vuint16_t CYCCNT:6;
    } B;
  } CYCTR;

  union {                              /* Slot Counter Channel A Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t SLOTCNTA:11;
    } B;
  } SLTCTAR;

  union {                              /* Slot Counter Channel B Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t SLOTCNTB:11;
    } B;
  } SLTCTBR;

  union {                              /* Rate Correction Value Register */
    vuint16_t R;
    struct {
      vuint16_t RATECORR:16;
    } B;
  } RTCORVR;

  union {                              /* Offset Correction Value Register */
    vuint16_t R;
    struct {
      vuint16_t OFFSETCORR:16;
    } B;
  } OFCORVR;

  union {                              /* Combined Interrupt Flag Register */
    vuint16_t R;
    struct {
      vuint16_t  :8;
      vuint16_t MIF:1;
      vuint16_t PRIF:1;
      vuint16_t CHIF:1;
      vuint16_t WUPIF:1;
      vuint16_t FAFBIF:1;
      vuint16_t FAFAIF:1;
      vuint16_t RBIF:1;
      vuint16_t TBIF:1;
    } B;
  } CIFR;

  union {                              /* System Memory Access Time-Out Register */
    vuint16_t R;
    struct {
      vuint16_t  :8;
      vuint16_t TIMEOUT:8;
    } B;
  } SYMATOR;

  union {                              /* Sync Frame Counter Register */
    vuint16_t R;
    struct {
      vuint16_t SFEVB:4;
      vuint16_t SFEVA:4;
      vuint16_t SFODB:4;
      vuint16_t SFODA:4;
    } B;
  } SFCNTR;

  union {                              /* Sync Frame Table Offset Register */
    vuint16_t R;
    struct {
      vuint16_t SFT_OFFSET:15;
      vuint16_t  :1;
    } B;
  } SFTOR;

  union {                              /* Sync Frame Table Configuration, Control, Status Register */
    vuint16_t R;
    struct {
      vuint16_t ELKT:1;
      vuint16_t OLKT:1;
      vuint16_t CYCNUM:6;
      vuint16_t ELKS:1;
      vuint16_t OLKS:1;
      vuint16_t EVAL:1;
      vuint16_t OVAL:1;
      vuint16_t  :1;
      vuint16_t OPT:1;
      vuint16_t SDVEN:1;
      vuint16_t SIDEN:1;
    } B;
  } SFTCCSR;

  union {                              /* Sync Frame ID Rejection Filter Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t SYNFRID:10;
    } B;
  } SFIDRFR;

  union {                              /* Sync Frame ID Acceptance Filter Value Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t FVAL:10;
    } B;
  } SFIDAFVR;

  union {                              /* Sync Frame ID Acceptance Filter Mask Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t FMSK:10;
    } B;
  } SFIDAFMR;

  union {                              /* Network Management Vector Register */
    vuint16_t R;
    struct {
      vuint16_t NMVP:16;
    } B;
  } NMVR[6];

  union {                              /* Network Management Vector Length Register */
    vuint16_t R;
    struct {
      vuint16_t  :12;
      vuint16_t NMVL:4;
    } B;
  } NMVLR;

  union {                              /* Timer Configuration and Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t T2_CFG:1;
      vuint16_t T2_REP:1;
      vuint16_t  :1;
      vuint16_t T2SP:1;
      vuint16_t T2TR:1;
      vuint16_t T2ST:1;
      vuint16_t  :3;
      vuint16_t T1_REP:1;
      vuint16_t  :1;
      vuint16_t T1SP:1;
      vuint16_t T1TR:1;
      vuint16_t T1ST:1;
    } B;
  } TICCR;

  union {                              /* Timer 1 Cycle Set Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t T1_CYC_VAL:6;
      vuint16_t  :2;
      vuint16_t T1_CYC_MSK:6;
    } B;
  } TI1CYSR;

  union {                              /* Timer 1 Macrotick Offset Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t T1_MTOFFSET:14;
    } B;
  } TI1MTOR;

  union {
    union {                            /* Timer 2 Configuration Register 0 (Absolute Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t  :2;
        vuint16_t T2CYCVAL:6;          /* Timer T2 Cycle Filter Mask */
        vuint16_t  :2;
        vuint16_t T2CYCMSK:6;          /* Timer T2 Cycle Filter Mask */
      } B;
    } ABS;
    union {                            /* Timer 2 Configuration Register 0 (Relative Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t T2MTCNT:16;          /* Timer T2 Macrotick High Word */
      } B;
    } REL;
  } TI2CR0;

  union {
    union {                            /* Timer 2 Configuration Register 1 (Absolute Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t  :2;
        vuint16_t T2MOFF:14;           /* Timer T2 Macrotick Offset */
      } B;
    } ABS;
    union {                            /* Timer 2 Configuration Register 1 (Relative Timer Configuration) */
      vuint16_t R;
      struct {
        vuint16_t T2MTCNT:16;
      } B;
    } REL;
  } TI2CR1;

  union {                              /* Slot Status Selection Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :1;
      vuint16_t SEL:2;
      vuint16_t  :1;
      vuint16_t SLOTNUMBER:11;
    } B;
  } SSSR;

  union {                              /* Slot Status Counter Condition Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :1;
      vuint16_t SEL:2;
      vuint16_t  :1;
      vuint16_t CNTCFG:2;
      vuint16_t MCY:1;
      vuint16_t VFR:1;
      vuint16_t SYF:1;
      vuint16_t NUF:1;
      vuint16_t SUF:1;
      vuint16_t STATUSMASK:4;
    } B;
  } SSCCR;

  union {                              /* Slot Status Register */
    vuint16_t R;
    struct {
      vuint16_t VFB:1;
      vuint16_t SYB:1;
      vuint16_t NFB:1;
      vuint16_t SUB:1;
      vuint16_t SEB:1;
      vuint16_t CEB:1;
      vuint16_t BVB:1;
      vuint16_t TCB:1;
      vuint16_t VFA:1;
      vuint16_t SYA:1;
      vuint16_t NFA:1;
      vuint16_t SUA:1;
      vuint16_t SEA:1;
      vuint16_t CEA:1;
      vuint16_t BVA:1;
      vuint16_t TCA:1;
    } B;
  } SSR[8];

  union {                              /* Slot Status Counter Register */
    vuint16_t R;
    struct {
      vuint16_t SLOTSTATUSCNT:16;
    } B;
  } SSCR[4];

  union {                              /* MTS A Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t MTE:1;
      vuint16_t  :1;
      vuint16_t CYCCNTMSK:6;
      vuint16_t  :2;
      vuint16_t CYCCNTVAL:6;
    } B;
  } MTSACFR;

  union {                              /* MTS B Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t MTE:1;
      vuint16_t  :1;
      vuint16_t CYCCNTMSK:6;
      vuint16_t  :2;
      vuint16_t CYCCNTVAL:6;
    } B;
  } MTSBCFR;

  union {                              /* Receive Shadow Buffer Index Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t  :1;
      vuint16_t SEL:2;
      vuint16_t  :4;
      vuint16_t RSBIDX:8;              /* RSBIDXA1/RSBIDXA2/RSBIDXB1/RSBIDXB2- Receive Shadow Buffer Index */
    } B;
  } RSBIR;

  union {                              /* Receive FIFO Watermark and Selection Register */
    vuint16_t R;
    struct {
      vuint16_t WM:8;                  /* WMA/WMB - Watermark */
      vuint16_t  :7;
      vuint16_t SEL:1;
    } B;
  } RFWMSR;

  union {                              /* Receive FIFO Start Index Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t SIDX:10;               /* SIDXA/SIDXB - Start Index */
    } B;
  } RFSIR;

  union {                              /* Receive FIFO Depth and Size Register */
    vuint16_t R;
    struct {
      vuint16_t FIFO_DEPTH:8;          /* FIFO_DEPTHA/FIFO_DEPTHB - FIFO Depth */
      vuint16_t  :1;
      vuint16_t ENTRY_SIZE:7;          /* ENTRY_SIZEA/ENTRY_SIZEB - Entry Size */
    } B;
  } RFDSR;

  union {                              /* Receive FIFO A Read Index Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t RDIDX:10;
    } B;
  } RFARIR;

  union {                              /* Receive FIFO B Read Index Register */
    vuint16_t R;
    struct {
      vuint16_t  :6;
      vuint16_t RDIDX:10;
    } B;
  } RFBRIR;

  union {                              /* Receive FIFO Message ID Acceptance Filter Value Register */
    vuint16_t R;
    struct {
      vuint16_t MIDAFVAL:16;           /* MIDAFVALA/MIDAFVALB - Message ID Acceptance Filter Value */
    } B;
  } RFMIDAFVR;

  union {                              /* Receive FIFO Message ID Acceptance Filter Mask Register */
    vuint16_t R;
    struct {
      vuint16_t MIDAFMSK:16;           /* MIDAFMSKA/MIDAFMSKB - Message ID Acceptance Filter Mask */
    } B;
  } RFMIDAFMR;

  union {                              /* Receive FIFO Frame ID Rejection Filter Value Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t FIDRFVAL:11;           /* FIDRFVALA/FIDRFVALB - Frame ID Rejection Filter Value */
    } B;
  } RFFIDRFVR;

  union {                              /* Receive FIFO Frame ID Rejection Filter Mask Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t FIDRFMSK:11;
    } B;
  } RFFIDRFMR;

  union {                              /* Receive FIFO Range Filter Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t WMD:1;
      vuint16_t IBD:1;
      vuint16_t SEL:2;
      vuint16_t  :1;
      vuint16_t SID:11;                /* Slot ID */
    } B;
  } RFRFCFR;

  union {                              /* Receive FIFO Range Filter Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :4;
      vuint16_t F3MD:1;
      vuint16_t F2MD:1;
      vuint16_t F1MD:1;
      vuint16_t F0MD:1;
      vuint16_t  :4;
      vuint16_t F3EN:1;
      vuint16_t F2EN:1;
      vuint16_t F1EN:1;
      vuint16_t F0EN:1;
    } B;
  } RFRFCTR;

  union {                              /* Last Dynamic Transmit Slot Channel A Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t LDYNTXSLOTA:11;
    } B;
  } LDTXSLAR;

  union {                              /* Last Dynamic Transmit Slot Channel B Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t LDYNTXSLOTB:11;
    } B;
  } LDTXSLBR;

  union {                              /* Protocol Configuration Register 0 */
    vuint16_t R;
    struct {
      vuint16_t action_point_offset:6;
      vuint16_t static_slot_length:10;
    } B;
  } PCR0;

  union {                              /* Protocol Configuration Register 1 */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t macro_after_first_static_slot:14;
    } B;
  } PCR1;

  union {                              /* Protocol Configuration Register 2 */
    vuint16_t R;
    struct {
      vuint16_t minislot_after_action_point:6;
      vuint16_t number_of_static_slots:10; /* gNumberOfStaticSlots */
    } B;
  } PCR2;

  union {                              /* Protocol Configuration Register 3 */
    vuint16_t R;
    struct {
      vuint16_t wakeup_symbol_rx_low:6;
      vuint16_t minislot_action_point_offset:5;
      vuint16_t coldstart_attempts:5;
    } B;
  } PCR3;

  union {                              /* Protocol Configuration Register 4 */
    vuint16_t R;
    struct {
      vuint16_t cas_rx_low_max:7;
      vuint16_t wakeup_symbol_rx_window:9;
    } B;
  } PCR4;

  union {                              /* Protocol Configuration Register 5 */
    vuint16_t R;
    struct {
      vuint16_t tss_transmitter:4;
      vuint16_t wakeup_symbol_tx_low:6;
      vuint16_t wakeup_symbol_rx_idle:6;
    } B;
  } PCR5;

  union {                              /* Protocol Configuration Register 6 */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t symbol_window_after_action_point:8;
      vuint16_t macro_initial_offset_a:7;
    } B;
  } PCR6;

  union {                              /* Protocol Configuration Register 7 */
    vuint16_t R;
    struct {
      vuint16_t decoding_correction_b:9;
      vuint16_t micro_per_macro_nom_half:7;
    } B;
  } PCR7;

  union {                              /* Protocol Configuration Register 8 */
    vuint16_t R;
    struct {
      vuint16_t max_without_clock_correction_fatal:4;
      vuint16_t max_without_clock_correction_passive:4;
      vuint16_t wakeup_symbol_tx_idle:8;
    } B;
  } PCR8;

  union {                              /* Protocol Configuration Register 9 */
    vuint16_t R;
    struct {
      vuint16_t minislot_exists:1;
      vuint16_t symbol_window_exists:1;
      vuint16_t offset_correction_out:14;
    } B;
  } PCR9;

  union {                              /* Protocol Configuration Register 10 */
    vuint16_t R;
    struct {
      vuint16_t single_slot_enabled:1;
      vuint16_t wakeup_channel:1;
      vuint16_t macro_per_cycle:14;
    } B;
  } PCR10;

  union {                              /* Protocol Configuration Register 11 */
    vuint16_t R;
    struct {
      vuint16_t key_slot_used_for_startup:1;
      vuint16_t key_slot_used_for_sync:1;
      vuint16_t offset_correction_start:14;
    } B;
  } PCR11;

  union {                              /* Protocol Configuration Register 12 */
    vuint16_t R;
    struct {
      vuint16_t allow_passive_to_active:5;
      vuint16_t key_slot_header_crc:11;
    } B;
  } PCR12;

  union {                              /* Protocol Configuration Register 13 */
    vuint16_t R;
    struct {
      vuint16_t first_minislot_action_point_offset:6;
      vuint16_t static_slot_after_action_point:10;
    } B;
  } PCR13;

  union {                              /* Protocol Configuration Register 14 */
    vuint16_t R;
    struct {
      vuint16_t rate_correction_out:11;
      vuint16_t listen_timeout:5;
    } B;
  } PCR14;

  union {                              /* Protocol Configuration Register 15 */
    vuint16_t R;
    struct {
      vuint16_t listen_timeout:16;
    } B;
  } PCR15;

  union {                              /* Protocol Configuration Register 16 */
    vuint16_t R;
    struct {
      vuint16_t macro_initial_offset_b:7;
      vuint16_t noise_listen_timeout:9;
    } B;
  } PCR16;

  union {                              /* Protocol Configuration Register 17 */
    vuint16_t R;
    struct {
      vuint16_t noise_listen_timeout:16;
    } B;
  } PCR17;

  union {                              /* Protocol Configuration Register 18 */
    vuint16_t R;
    struct {
      vuint16_t wakeup_pattern:6;
      vuint16_t key_slot_id:10;
    } B;
  } PCR18;

  union {                              /* Protocol Configuration Register 19 */
    vuint16_t R;
    struct {
      vuint16_t decoding_correction_a:9;
      vuint16_t payload_length_static:7;
    } B;
  } PCR19;

  union {                              /* Protocol Configuration Register 20 */
    vuint16_t R;
    struct {
      vuint16_t micro_initial_offset_b:8;
      vuint16_t micro_initial_offset_a:8;
    } B;
  } PCR20;

  union {                              /* Protocol Configuration Register 21 */
    vuint16_t R;
    struct {
      vuint16_t extern_rate_correction:3;
      vuint16_t latest_tx:13;
    } B;
  } PCR21;

  union {                              /* Protocol Configuration Register 22 */
    vuint16_t R;
    struct {
      vuint16_t  :1;                   /* Reserved bit, will not be changed. Application must not write any value different from the reset value. */
      vuint16_t comp_accepted_startup_range_a:11;
      vuint16_t micro_per_cycle:4;
    } B;
  } PCR22;

  union {                              /* Protocol Configuration Register 23 */
    vuint16_t R;
    struct {
      vuint16_t micro_per_cycle:16;
    } B;
  } PCR23;

  union {                              /* Protocol Configuration Register 24 */
    vuint16_t R;
    struct {
      vuint16_t cluster_drift_damping:5;
      vuint16_t max_payload_length_dynamic:7;
      vuint16_t micro_per_cycle_min:4;
    } B;
  } PCR24;

  union {                              /* Protocol Configuration Register 25 */
    vuint16_t R;
    struct {
      vuint16_t micro_per_cycle_min:16;
    } B;
  } PCR25;

  union {                              /* Protocol Configuration Register 26 */
    vuint16_t R;
    struct {
      vuint16_t allow_halt_due_to_clock:1;
      vuint16_t comp_accepted_startup_range_b:11;
      vuint16_t micro_per_cycle_max:4;
    } B;
  } PCR26;

  union {                              /* Protocol Configuration Register 27 */
    vuint16_t R;
    struct {
      vuint16_t micro_per_cycle_max:16;
    } B;
  } PCR27;

  union {                              /* Protocol Configuration Register 28 */
    vuint16_t R;
    struct {
      vuint16_t dynamic_slot_idle_phase:2;
      vuint16_t macro_after_offset_correction:14;
    } B;
  } PCR28;

  union {                              /* Protocol Configuration Register 29 */
    vuint16_t R;
    struct {
      vuint16_t extern_offset_correction:3;
      vuint16_t minislots_max:13;
    } B;
  } PCR29;

  union {                              /* Protocol Configuration Register 30 */
    vuint16_t R;
    struct {
      vuint16_t  :12;
      vuint16_t sync_node_max:4;
    } B;
  } PCR30;

  union {                              /* StopWatch Count Register */
    vuint16_t R;
    struct {
      vuint16_t STPW:16;               /* StopWatch Count Register */
    } B;
  } STPWR;

  uint8_t FR_reserved1[2];
  union {                              /* Protocol Event Output Enable and StopWatch Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :7;
      vuint16_t STPW_EN:1;             /* Stopwatch count Enable */
      vuint16_t  :5;
      vuint16_t TIM2_EE:1;
      vuint16_t TIM1_EE:1;
      vuint16_t CYC_EE:1;
    } B;
  } PEOER;

  uint8_t FR_reserved2[2];
  union {                              /* Receive FIFO Start Data Offset Register */
    vuint16_t R;
    struct {
      vuint16_t SDO:16;                /* SDOA/SDOB - Start Data Field Offset */
    } B;
  } RFSDOR;

  union {                              /* Receive FIFO System Memory Base Address High Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:16;
    } B;
  } RFSYMBADHR;

  union {                              /* Receive FIFO System Memory Base Address Low Register */
    vuint16_t R;
    struct {
      vuint16_t SMBA:12;
      vuint16_t  :4;
    } B;
  } RFSYMBADLR;

  union {                              /* Receive FIFO Periodic Timer Register */
    vuint16_t R;
    struct {
      vuint16_t  :2;
      vuint16_t PTD:14;
    } B;
  } RFPTR;

  union {                              /* Receive FIFO Fill Level and POP Count Register */
    vuint16_t R;
    struct {
      vuint16_t FLB_or_PCB:8;
      vuint16_t FLA_or_PCA:8;
    } B;
  } RFFLPCR;

  union {                              /* ECC Error Interrupt Flag and Enable Register */
    vuint16_t R;
    struct {
      vuint16_t LRNE_OF:1;
      vuint16_t LRCE_OF:1;
      vuint16_t DRNE_OF:1;
      vuint16_t DRCE_OF:1;
      vuint16_t LRNE_IF:1;
      vuint16_t LRCE_IF:1;
      vuint16_t DRNE_IF:1;
      vuint16_t DRCE_IF:1;
      vuint16_t  :4;
      vuint16_t LRNE_IE:1;
      vuint16_t LRCE_IE:1;
      vuint16_t DRNE_IE:1;
      vuint16_t DRCE_IE:1;
    } B;
  } EEIFER;

  union {                              /* ECC Error Report and Injection Control Register */
    vuint16_t R;
    struct {
      vuint16_t BSY:1;
      vuint16_t  :5;
      vuint16_t ERS:2;
      vuint16_t  :3;
      vuint16_t ERM:1;
      vuint16_t  :2;
      vuint16_t EIM:1;
      vuint16_t EIE:1;
    } B;
  } EERICR;

  union {                              /* ECC Error Report Address Register */
    vuint16_t R;
    struct {
      vuint16_t MID:1;
      vuint16_t BANK:3;
      vuint16_t ADDR:12;
    } B;
  } EERAR;

  union {                              /* ECC Error Report Data Register */
    vuint16_t R;
    struct {
      vuint16_t DATA:16;
    } B;
  } EERDR;

  union {                              /* ECC Error Report Code Register */
    vuint16_t R;
    struct {
      vuint16_t  :11;
      vuint16_t CODE:5;
    } B;
  } EERCR;

  union {                              /* ECC Error Injection Address Register */
    vuint16_t R;
    struct {
      vuint16_t MID:1;
      vuint16_t BANK:3;
      vuint16_t ADDR:12;
    } B;
  } EEIAR;

  union {                              /* ECC Error Injection Data Register */
    vuint16_t R;
    struct {
      vuint16_t DATA:16;
    } B;
  } EEIDR;

  union {                              /* ECC Error Injection Code Register */
    vuint16_t R;
    struct {
      vuint16_t  :11;
      vuint16_t CODE:5;
    } B;
  } EEICR;

  uint8_t FR_reserved3[1792];
  struct {
    union {                            /* Message Buffer Configuration, Control, Status Register */
      vuint16_t R;
      struct {
        vuint16_t  :3;
        vuint16_t MTD:1;
        vuint16_t CMT:1;
        vuint16_t EDT:1;
        vuint16_t LCKT:1;
        vuint16_t MBIE:1;
        vuint16_t  :3;
        vuint16_t DUP:1;
        vuint16_t DVAL:1;
        vuint16_t EDS:1;
        vuint16_t LCKS:1;
        vuint16_t MBIF:1;
      } B;
    } CCSR;
    union {                            /* Message Buffer Cycle Counter Filter Register */
      vuint16_t R;
      struct {
        vuint16_t MTM:1;
        vuint16_t CHA:1;
        vuint16_t CHB:1;
        vuint16_t CCFE:1;
        vuint16_t CCFMSK:6;
        vuint16_t CCFVAL:6;
      } B;
    } CCFR;
    union {                            /* Message Buffer Frame ID Register */
      vuint16_t R;
      struct {
        vuint16_t  :5;
        vuint16_t FID:11;
      } B;
    } FIDR;
    union {                            /* Message Buffer Index Register */
      vuint16_t R;
      struct {
        vuint16_t  :8;
        vuint16_t MBIDX:8;
      } B;
    } IDXR;
  } MB[128];

  uint8_t FR_reserved4[1024];
  union {                              /* Message Buffer Data Field Offset Register */
    vuint16_t R;
    struct {
      vuint16_t MBDO:16;
    } B;
  } MBDOR[132];

  union {                              /* LRAM ECC Error Test Register */
    vuint16_t R;
    struct {
      vuint16_t LEETD:16;
    } B;
  } LEETR[6];
};


/* ============================================================================
   =============================== Module: GTMINT =============================
   ============================================================================ */

struct GTMINT_tag {
  uint8_t GTMINT_reserved0[192];
  union {                              /* GTM Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t MDIS:1;                /* [BLG_GTMW_007] [Covers: Saf1461] Saf1276 - Safety-critical MDIS {end} Module Disable. */
      vuint32_t  :13;
      vuint32_t AEISREN:1;             /* [BLG_GTMW_007] [Covers: Saf1461] Saf1276 - Safety-critical AEISREN [end] AEI interface soft-reset control enable . */
      vuint32_t  :1;
      vuint32_t STPS:1;                /* [BLG_GTMW_007] [Covers: Saf1461] Saf1276 - Safety-critical STPS [end] Stop Mode Status . */
      vuint32_t  :14;
    } B;
  } GTMMCR;

  uint8_t GTMINT_reserved1[4];
  union {                              /* GTM Interrupts Clear Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t INTCLR_PTR:10;         /* [BLG_GTMW_007] [Covers: Saf1461] Saf1276 - Safety-critical INTCLR_PTR {end} Interrupt Clear Pointer. */
    } B;
  } GTMINTCLR;

  union {                              /* GTM AEI Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t AEISRST:1;             /* [BLG_GTMW_007] [Covers: Saf1461] Saf1276 - Safety-critical AEISRST {end} AEI interface soft-reset control . */
    } B;
  } GTMAEICR;
};


/* ============================================================================
   =============================== Module: I2C ================================
   ============================================================================ */

struct I2C_tag {
  union {                              /* I2C Bus Address Register */
    vuint8_t R;
    struct {
      vuint8_t ADR:7;
      vuint8_t  :1;
    } B;
  } IBAD;

  union {                              /* I2C Bus Frequency Divider Register */
    vuint8_t R;
    struct {
      vuint8_t IBC:8;
    } B;
  } IBFD;

  union {                              /* I2C Bus Control Register */
    vuint8_t R;
    struct {
      vuint8_t MDIS:1;
      vuint8_t IBIE:1;
      vuint8_t MSSL:1;
      vuint8_t TXRX:1;
      vuint8_t NOACK:1;
      vuint8_t RSTA:1;
      vuint8_t DMAEN:1;
      vuint8_t  :1;
    } B;
  } IBCR;

  union {                              /* I2C Bus Status Register */
    vuint8_t R;
    struct {
      vuint8_t TCF:1;
      vuint8_t IAAS:1;
      vuint8_t IBB:1;
      vuint8_t IBAL:1;
      vuint8_t  :1;
      vuint8_t SRW:1;
      vuint8_t IBIF:1;
      vuint8_t RXAK:1;
    } B;
  } IBSR;

  union {                              /* I2C Bus Data I/O Register */
    vuint8_t R;
    struct {
      vuint8_t DATA:8;
    } B;
  } IBDR;

  union {                              /* I2C Bus Interrupt Config Register */
    vuint8_t R;
    struct {
      vuint8_t BIIE:1;
      vuint8_t  :3;
      vuint8_t  :1;
      vuint8_t  :1;
      vuint8_t  :1;
      vuint8_t  :1;
    } B;
  } IBIC;

  union {                              /* I2C Bus Debug Register */
    vuint8_t R;
    struct {
      vuint8_t  :6;
      vuint8_t IPG_DEBUG_HALTED:1;
      vuint8_t IPG_DEBUG_EN:1;
    } B;
  } IBDBG;
};


/* ============================================================================
   =============================== Module: IMA ================================
   ============================================================================ */

struct IMA_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t READ:1;
    } B;
  } CTRL;

  union {                              /* Enable Access Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t EN:1;
    } B;
  } ENABLE;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t WRITE_LOCK:1;
      vuint32_t  :7;
      vuint32_t READ_LOCK:1;
    } B;
  } STATUS;

  union {                              /* RAM Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ROW_SLCT:13;
      vuint32_t  :10;
      vuint32_t ARRAY_SLCT:6;
    } B;
  } SLCT;

  union {                              /* Write Unlock Register */
    vuint32_t R;
    struct {
      vuint32_t WRITE_KEY:32;
    } B;
  } WRITE_UNLOCK;

  union {                              /* Read Unlock Register */
    vuint32_t R;
    struct {
      vuint32_t READ_KEY:32;
    } B;
  } READ_UNLOCK;

  uint8_t IMA_reserved0[20];
  union {                              /* RAM Write Data Register 4 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_4:32;
    } B;
  } WRITE_DATA_4;

  union {                              /* RAM Write Data Register 3 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_3:32;
    } B;
  } WRITE_DATA_3;

  union {                              /* RAM Write Data Register 2 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_2:32;
    } B;
  } WRITE_DATA_2;

  union {                              /* RAM Write Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_1:32;
    } B;
  } WRITE_DATA_1;

  union {                              /* RAM Write Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t WRITE_0:32;
    } B;
  } WRITE_DATA_0;

  uint8_t IMA_reserved1[12];
  union {                              /* RAM Read Data Register 4 */
    vuint32_t R;
    struct {
      vuint32_t READ_4:32;
    } B;
  } READ_DATA_4;

  union {                              /* RAM Read Data Register 3 */
    vuint32_t R;
    struct {
      vuint32_t READ_3:32;
    } B;
  } READ_DATA_3;

  union {                              /* RAM Read Data Register 2 */
    vuint32_t R;
    struct {
      vuint32_t READ_2:32;
    } B;
  } READ_DATA_2;

  union {                              /* RAM Read Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t READ_1:32;
    } B;
  } READ_DATA_1;

  union {                              /* RAM Read Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t READ_0:32;
    } B;
  } READ_DATA_0;
};


/* ============================================================================
   =============================== Module: INTC ===============================
   ============================================================================ */

struct INTC_tag {
  union {                              /* INTC Block Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t HVEN3:1;
      vuint32_t  :3;
      vuint32_t HVEN2:1;
      vuint32_t  :3;
      vuint32_t HVEN1:1;
      vuint32_t  :3;
      vuint32_t HVEN0:1;
    } B;
  } MCR;

  union {                              /* INTC Master Protection Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ID:2;
      vuint32_t  :3;
      vuint32_t MPROT:1;
    } B;
  } MPROT;

  uint8_t INTC_reserved0[8];
  union {                              /* INTC Current Priority Register for Processor n */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t PRI:6;
    } B;
  } CPR[4];

  union {                              /* INTC Interrupt Acknowledge Register for Processor 0 */
    vuint32_t R;
    struct {
      vuint32_t VTBA:20;
      vuint32_t INTVEC:10;
      vuint32_t  :2;
    } B;
  } IACKR_PRC0;

  union {                              /* INTC Interrupt Acknowledge Register for Processor 1 */
    vuint32_t R;
    struct {
      vuint32_t VTBA:20;
      vuint32_t INTVEC:10;
      vuint32_t  :2;
    } B;
  } IACKR_PRC1;

  union {                              /* INTC Interrupt Acknowledge Register for Processor 2 */
    vuint32_t R;
    struct {
      vuint32_t VTBA:20;
      vuint32_t INTVEC:10;
      vuint32_t  :2;
    } B;
  } IACKR_PRC2;

  union {                              /* INTC Interrupt Acknowledge Register for Processor 3 */
    vuint32_t R;
    struct {
      vuint32_t VTBA:20;
      vuint32_t INTVEC:10;
      vuint32_t  :2;
    } B;
  } IACKR_PRC3;

  union {                              /* INTC End Of Interrupt Register for Processor 0 */
    vuint32_t R;
    struct {
      vuint32_t EOI:32;
    } B;
  } EOIR_PRC0;

  union {                              /* INTC End Of Interrupt Register for Processor 1 */
    vuint32_t R;
    struct {
      vuint32_t EOI:32;
    } B;
  } EOIR_PRC1;

  union {                              /* INTC End Of Interrupt Register for Processor 2 */
    vuint32_t R;
    struct {
      vuint32_t EOI:32;
    } B;
  } EOIR_PRC2;

  union {                              /* INTC End Of Interrupt Register for Processor 3 */
    vuint32_t R;
    struct {
      vuint32_t EOI:32;
    } B;
  } EOIR_PRC3;

  union {                              /* INTC Software Set/Clear Interrupt Register */
    vuint8_t R;
    struct {
      vuint8_t  :6;
      vuint8_t SET:1;
      vuint8_t CLR:1;
    } B;
  } SSCIR[32];

  union {                              /* INTC Priority Select Register */
    vuint16_t R;
    struct {
      vuint16_t PRC_SEL:4;
      vuint16_t  :3;
      vuint16_t SWTN:1;
      vuint16_t  :2;
      vuint16_t PRI:6;
    } B;
  } PSR[1024];
};


/* ============================================================================
   =============================== Module: IRCOSC =============================
   ============================================================================ */

struct IRCOSC_tag {
  union {                              /* IRCOSC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t  :1;
      vuint32_t  :3;
      vuint32_t USER_TRIM:5;
      vuint32_t  :3;
      vuint32_t  :5;
      vuint32_t  :2;
      vuint32_t  :1;
      vuint32_t  :5;
    } B;
  } CTL;
};


/* ============================================================================
   =============================== Module: JDC ================================
   ============================================================================ */

struct JDC_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t JIN_IEN:1;
      vuint32_t  :15;
      vuint32_t JOUT_IEN:1;
    } B;
  } MCR;

  union {                              /* Module Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t JIN_RDY:1;
      vuint32_t  :1;
      vuint32_t JIN_INT:1;
      vuint32_t  :13;
      vuint32_t JOUT_RDY:1;
      vuint32_t  :1;
      vuint32_t JOUT_INT:1;
    } B;
  } MSR;

  union {                              /* JTAG Output Data Register */
    vuint32_t R;
    struct {
      vuint32_t Data:32;
    } B;
  } JOUT_IPS;

  union {                              /* JTAG Input Data Register */
    vuint32_t R;
    struct {
      vuint32_t Data:32;
    } B;
  } JIN_IPS;
};


/* ============================================================================
   =============================== Module: JTAGM ==============================
   ============================================================================ */

struct JTAGM_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t SWRESET:1;
      vuint32_t evto0_sense:2;
      vuint32_t evto1_sense:2;
      vuint32_t evto_IE:1;
      vuint32_t evti0_assert:1;
      vuint32_t evti1_assert:1;
      vuint32_t  :10;
      vuint32_t inter_jtag_frame_timer:6;
      vuint32_t  :1;
      vuint32_t SIE:1;
      vuint32_t IIE:1;
      vuint32_t TCKSEL:3;
      vuint32_t jtagm_JCOMP:1;
      vuint32_t DTM:1;
    } B;
  } MCR;

  union {                              /* Status Register */
    vuint32_t R;
    struct {
      vuint32_t Overrun:1;
      vuint32_t  :1;
      vuint32_t TXGOOD:1;
      vuint32_t TXERROR:1;
      vuint32_t RXOVFL:1;
      vuint32_t INVFPS:1;
      vuint32_t INVICLC:1;
      vuint32_t ILLLCT:1;
      vuint32_t  :1;
      vuint32_t LVDSEN:1;
      vuint32_t JTAGEN:1;
      vuint32_t LVDSSAFE:1;
      vuint32_t JTAGSAFE:1;
      vuint32_t LVDSESC:1;
      vuint32_t LFASTEN:1;
      vuint32_t TOOL:1;
      vuint32_t evto0_edge:1;
      vuint32_t evto1_edge:1;
      vuint32_t SPU_INT_CLR:1;
      vuint32_t SPU_INT:1;
      vuint32_t CRC_err:1;
      vuint32_t Nexus_err:1;
      vuint32_t Idle:1;
      vuint32_t NR:1;
      vuint32_t CRC:8;
    } B;
  } SR;

  union {                              /* Data Out Register 0 */
    vuint32_t R;
    struct {
      vuint32_t TMS_HIGH:32;
    } B;
  } DOR0;

  union {                              /* Data Out Register 1 */
    vuint32_t R;
    struct {
      vuint32_t TMS_LOW:28;
      vuint32_t  :4;
    } B;
  } DOR1;

  union {                              /* Data Out Register 2 */
    vuint32_t R;
    struct {
      vuint32_t TDI_HIGH:32;
    } B;
  } DOR2;

  union {                              /* Data Out Register 3 */
    vuint32_t R;
    struct {
      vuint32_t TDI_LOW:28;
      vuint32_t  :3;
      vuint32_t Send:1;
    } B;
  } DOR3;

  union {                              /* Receive CRC Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t CRC:8;
    } B;
  } RxCRC;

  union {                              /* Data Input Register 0 */
    vuint32_t R;
    struct {
      vuint32_t TDO_LOW:32;
    } B;
  } DIR0;

  union {                              /* Data Input Register 1 */
    vuint32_t R;
    struct {
      vuint32_t TDO_HIGH:28;
      vuint32_t  :4;
    } B;
  } DIR1;
};


/* ============================================================================
   =============================== Module: LFAST ==============================
   ============================================================================ */

struct LFAST_tag {
  union {                              /* LFAST Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t MSEN:1;
      vuint32_t  :6;
      vuint32_t IPGDBG:1;
      vuint32_t  :7;
      vuint32_t LSSEL:1;
      vuint32_t DRFEN:1;
      vuint32_t RXEN:1;
      vuint32_t TXEN:1;
      vuint32_t  :8;
      vuint32_t TXARBD:1;
      vuint32_t CTSEN:1;
      vuint32_t  :1;
      vuint32_t DRFRST:1;
      vuint32_t DATAEN:1;
    } B;
  } MCR;

  union {                              /* LFAST Speed Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t DRMD:1;
      vuint32_t  :7;
      vuint32_t RDR:1;
      vuint32_t  :7;
      vuint32_t TDR:1;
    } B;
  } SCR;

  union {                              /* LFAST Correlator Control Register */
    vuint32_t R;
    struct {
      vuint32_t SMPSEL:8;
      vuint32_t  :6;
      vuint32_t  :2;
      vuint32_t  :12;
      vuint32_t CORRTH:3;
      vuint32_t PHSSEL:1;
    } B;
  } COCR;

  union {                              /* LFAST Test Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t CLKTST:1;
      vuint32_t LPON:1;
      vuint32_t  :5;
      vuint32_t LPMOD:3;
      vuint32_t LPFRMTH:16;
    } B;
  } TMCR;

  union {                              /* LFAST Auto Loopback Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t LPCNTEN:1;
      vuint32_t LPFMCNT:16;
    } B;
  } ALCR;

  union {                              /* LFAST Rate Change Delay Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DRCNT:4;
      vuint32_t  :16;
    } B;
  } RCDCR;

  union {                              /* LFAST Wakeup Delay Control Register */
    vuint32_t R;
    struct {
      vuint32_t HSCNT:8;
      vuint32_t  :4;
      vuint32_t LSCNT:4;
      vuint32_t HWKCNT:8;
      vuint32_t  :4;
      vuint32_t LWKCNT:4;
    } B;
  } SLCR;

  union {                              /* LFAST ICLC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t ICLCSEQ:1;
      vuint32_t SNDICLC:1;
      vuint32_t  :8;
      vuint32_t ICLCPLD:8;
    } B;
  } ICR;

  union {                              /* LFAST Ping Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t PNGREQ:1;
      vuint32_t PNGAUTO:1;
      vuint32_t  :7;
      vuint32_t PNGPYLD:8;
    } B;
  } PICR;

  uint8_t LFAST_reserved0[8];
  union {                              /* LFAST Rx FIFO CTS Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t RCTSMX:6;
      vuint32_t  :10;
      vuint32_t RCTSMN:6;
    } B;
  } RFCR;

  union {                              /* LFAST Tx Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t TXIIE:1;
      vuint32_t TXOVIE:1;
      vuint32_t  :11;
      vuint32_t TXPNGIE:1;
      vuint32_t  :1;
      vuint32_t TXUNSIE:1;
      vuint32_t TXICLCIE:1;
      vuint32_t TXDTIE:1;
    } B;
  } TIER;

  union {                              /* LFAST Rx Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t RXUOIE:1;
      vuint32_t RXMNIE:1;
      vuint32_t RXMXIE:1;
      vuint32_t RXUFIE:1;
      vuint32_t RXOFIE:1;
      vuint32_t RXSZIE:1;
      vuint32_t RXICIE:1;
      vuint32_t RXLCEIE:1;
      vuint32_t  :12;
      vuint32_t RXCTSIE:1;
      vuint32_t RXDIE:1;
      vuint32_t RXUNSIE:1;
      vuint32_t  :1;
    } B;
  } RIER;

  union {                              /* LFAST Rx ICLC Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t ICPFIE:1;
      vuint32_t ICPSIE:1;
      vuint32_t ICPRIE:1;
      vuint32_t ICTOIE:1;
      vuint32_t ICLPIE:1;
      vuint32_t ICCTIE:1;
      vuint32_t ICTDIE:1;
      vuint32_t ICTEIE:1;
      vuint32_t ICRFIE:1;
      vuint32_t ICRSIE:1;
      vuint32_t ICTFIE:1;
      vuint32_t ICTSIE:1;
      vuint32_t ICPOFIE:1;
      vuint32_t ICPONIE:1;
    } B;
  } RIIER;

  union {                              /* LFAST PLL Control Register */
    vuint32_t R;
    struct {
      vuint32_t IPTMOD:3;
      vuint32_t  :11;
      vuint32_t SWPOFF:1;
      vuint32_t SWPON:1;
      vuint32_t REFINV:1;
      vuint32_t LPCFG:2;
      vuint32_t  :2;
      vuint32_t PLCKCW:2;
      vuint32_t FDIVEN:1;
      vuint32_t FBDIV:6;
      vuint32_t PREDIV:2;
    } B;
  } PLLCR;

  union {                              /* LFAST LVDS Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t SWWKLD:1;
      vuint32_t SWSLPLD:1;
      vuint32_t SWWKLR:1;
      vuint32_t SWSLPLR:1;
      vuint32_t SWOFFLD:1;
      vuint32_t SWONLD:1;
      vuint32_t SWOFFLR:1;
      vuint32_t SWONLR:1;
      vuint32_t LVRXOFF:1;
      vuint32_t LVTXOE:1;
      vuint32_t TXCMUX:1;
      vuint32_t LVRFEN:1;
      vuint32_t LVLPEN:1;              /* Tx LVDS internal loopback enable */
      vuint32_t  :5;
      vuint32_t LVRXOP:3;
      vuint32_t  :1;
      vuint32_t LVCKSS:1;
      vuint32_t LVCKP:1;
    } B;
  } LCR;

  union {                              /* LFAST Unsolicited Tx Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t USNDRQ:1;
      vuint32_t  :9;
      vuint32_t UNSHDR:7;
    } B;
  } UNSTCR;

  union {                              /* LFAST Unsolicited Tx Data Registers */
    vuint32_t R;
    struct {
      vuint32_t UNTXD:32;
    } B;
  } UNSTDR[9];

  uint8_t LFAST_reserved1[20];
  union {                              /* LFAST Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t DUALMD:1;
      vuint32_t  :12;
      vuint32_t LRMD:1;
      vuint32_t LDSM:1;
      vuint32_t DRSM:1;
      vuint32_t  :11;
      vuint32_t LPTXDN:1;
      vuint32_t LPFPDV:1;
      vuint32_t LPCPDV:1;
      vuint32_t LPCHDV:1;
      vuint32_t LPCSDV:1;
    } B;
  } GSR;

  union {                              /* LFAST Ping Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RXPNGD:8;
    } B;
  } PISR;

  uint8_t LFAST_reserved2[12];
  union {                              /* LFAST Data Frame Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t RXDCNT:6;
      vuint32_t  :5;
      vuint32_t RXFCNT:3;
      vuint32_t  :2;
      vuint32_t TXDCNT:6;
      vuint32_t  :5;
      vuint32_t TXFCNT:3;
    } B;
  } DFSR;

  union {                              /* LFAST Tx Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t TXIEF:1;
      vuint32_t TXOVF:1;
      vuint32_t  :11;
      vuint32_t TXPNGF:1;
      vuint32_t  :1;
      vuint32_t TXUNSF:1;
      vuint32_t TXICLCF:1;
      vuint32_t TXDTF:1;
    } B;
  } TISR;

  union {                              /* LFAST Rx Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t RXUOF:1;
      vuint32_t RXMNF:1;
      vuint32_t RXMXF:1;
      vuint32_t RXUFF:1;
      vuint32_t RXOFF:1;
      vuint32_t RXSZF:1;
      vuint32_t RXICF:1;
      vuint32_t RXLCEF:1;
      vuint32_t  :12;
      vuint32_t RXCTSF:1;
      vuint32_t RXDF:1;
      vuint32_t RXUNSF:1;
      vuint32_t  :1;
    } B;
  } RISR;

  union {                              /* LFAST Rx ICLC Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t ICPFF:1;
      vuint32_t ICPSF:1;
      vuint32_t ICPRF:1;
      vuint32_t ICTOF:1;
      vuint32_t ICLPF:1;
      vuint32_t ICCTF:1;
      vuint32_t ICTDF:1;
      vuint32_t ICTEF:1;
      vuint32_t ICRFF:1;
      vuint32_t ICRSF:1;
      vuint32_t ICTFF:1;
      vuint32_t ICTSF:1;
      vuint32_t ICPOFF:1;
      vuint32_t ICPONF:1;
    } B;
  } RIISR;

  union {                              /* LFAST PLL and LVDS Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t PLLDIS:1;
      vuint32_t PLDCR:1;
      vuint32_t  :12;
      vuint32_t LRSLPS:1;
      vuint32_t LDSLPS:1;
      vuint32_t LDPDS:1;
      vuint32_t LRPDS:1;
    } B;
  } PLLLSR;

  union {                              /* LFAST Unsolicited Rx Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t URXDV:1;
      vuint32_t  :5;
      vuint32_t URPCNT:3;
    } B;
  } UNSRSR;

  union {                              /* LFAST Unsolicited Rx Data Register */
    vuint32_t R;
    struct {
      vuint32_t UNRXD:32;
    } B;
  } UNSRDR[9];
};


/* ============================================================================
   =============================== Module: LINFlexD ===========================
   ============================================================================ */

struct LINFLEX_tag {
  union {                              /* LIN Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CCD:1;
      vuint32_t CFD:1;
      vuint32_t LASE:1;
      vuint32_t /* AUTOWU */AWUM:1;
      vuint32_t MBL:4;
      vuint32_t BF:1;
      vuint32_t SLFM:1; /* added for compatibility reasons, not part of 5777 */
      vuint32_t LBKM:1;
      vuint32_t MME:1;
      vuint32_t /* SSBL */SBDT:1;
      vuint32_t RBLM:1;
      vuint32_t SLEEP:1;
      vuint32_t INIT:1;
    } B;
  } LINCR1;

  union {                              /* LIN Interrupt enable register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZIE:1;
      vuint32_t OCIE:1;
      vuint32_t BEIE:1;
      vuint32_t CEIE:1;
      vuint32_t HEIE:1;
      vuint32_t  :2;
      vuint32_t FEIE:1;
      vuint32_t BOIE:1;
      vuint32_t LSIE:1;
      vuint32_t WUIE:1;
      vuint32_t DBFIE:1;
      vuint32_t DBEIETOIE:1;
      vuint32_t DRIE:1;
      vuint32_t DTIE:1;
      vuint32_t HRIE:1;
    } B;
  } LINIER;

  union {                              /* LIN Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t AUTOSYNC_COMP:1;
      vuint32_t RDC:3;
      vuint32_t LINS:4;                /* LIN state */
      vuint32_t  :2;
      vuint32_t RMB:1;
      vuint32_t DRBNE:1;
      vuint32_t /* RXbusy */RBSY:1;
      vuint32_t RDI:1;
      vuint32_t WUF:1;
      vuint32_t DBFF:1;
      vuint32_t DBEF:1;
      vuint32_t DRF:1;
      vuint32_t DTF:1;
      vuint32_t HRF:1;
    } B;
  } LINSR;

  union {                              /* LIN Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZF:1;
      vuint32_t OCF:1;
      vuint32_t BEF:1;
      vuint32_t CEF:1;
      vuint32_t SFEF:1;
      vuint32_t /* SDEF */BDEF:1;
      vuint32_t IDPEF:1;
      vuint32_t FEF:1;
      vuint32_t BOF:1;
      vuint32_t  :6;
      vuint32_t NF:1;
    } B;
  } LINESR;

  union {                              /* UART Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t MIS:1;
      vuint32_t CSP:3;
      vuint32_t OSR:4;
      vuint32_t ROSE:1;
      vuint32_t NEF:3;
      vuint32_t DTU_PCETX:1;           /* Disable Timeout in UART mode/Parity transmission and checking */
      vuint32_t SBUR:2;
      vuint32_t WLS:1;
      vuint32_t TDFL_TFC:3;
      vuint32_t RDFL_RFC:3;
      vuint32_t RFBM:1;
      vuint32_t TFBM:1;
      vuint32_t WL1:1;
      vuint32_t PC1:1;
      vuint32_t RxEn:1;
      vuint32_t TxEn:1;
      vuint32_t PC0:1;
      vuint32_t PCE:1;
      vuint32_t WL0:1;
      vuint32_t UART:1;
    } B;
  } UARTCR;

  union {                              /* UART Mode Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZF:1;
      vuint32_t OCF:1;
      vuint32_t PE:4;
      vuint32_t RMB:1;
      vuint32_t FEF:1;
      vuint32_t BOF:1;
      vuint32_t RDI:1;
      vuint32_t WUF:1;
      vuint32_t RFNE:1;
      vuint32_t TO:1;
      vuint32_t DRFRFE:1;
      vuint32_t DTFTFF:1;
      vuint32_t NF:1;
    } B;
  } UARTSR;

  union {                              /* LIN Time-Out Control Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t /* MODE */LTOM:1;
      vuint32_t IOT:1;
      vuint32_t TOCE:1;
      vuint32_t CNT:8;
    } B;
  } LINTCSR;

  union {                              /* LIN Output Compare Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t OC2:8;
      vuint32_t OC1:8;
    } B;
  } LINOCR;

  union {                              /* LIN Time-Out Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t RTO:4;
      vuint32_t  :1;
      vuint32_t HTO:7;
    } B;
  } LINTOCR;

  union {                              /* LIN Fractional Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t /* FBR */DIV_F:4;
    } B;
  } LINFBRR;

  union {                              /* LIN Integer Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t /* IBR */DIV_M:20;
    } B;
  } LINIBRR;

  union {                              /* LIN Checksum Field Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t CF:8;
    } B;
  } LINCFR;

  union {                              /* LIN Control Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TBDE:1;
      vuint32_t IOBE:1;
      vuint32_t IOPE:1;
      vuint32_t WURQ:1;
      vuint32_t DDRQ:1;
      vuint32_t DTRQ:1;
      vuint32_t ABRQ:1;
      vuint32_t HTRQ:1;
      vuint32_t  :8;
    } B;
  } LINCR2;

  union {                              /* Buffer Identifier Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DFL:6;
      vuint32_t DIR:1;
      vuint32_t CCS:1;
      vuint32_t  :2;
      vuint32_t ID:6;
    } B;
  } BIDR;

  union {                              /* Buffer Data Register Least Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA3:8;
      vuint32_t DATA2:8;
      vuint32_t DATA1:8;
      vuint32_t DATA0:8;
    } B;
  } BDRL;

  union {                              /* Buffer Data Register Most Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA7:8;
      vuint32_t DATA6:8;
      vuint32_t DATA5:8;
      vuint32_t DATA4:8;
    } B;
  } BDRM;

  union {                              /* Identifier Filter Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FACT:16;
    } B;
  } IFER;

  union {                              /* Identifier Filter Match Index */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t IFMI:5;
    } B;
  } IFMI;

  union {                              /* Identifier Filter Mode Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t IFM:8;
    } B;
  } IFMR;

  union {                              /* Identifier Filter Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DFL:6;                 /* Data Field Length */
      vuint32_t DIR:1;                 /* Direction */
      vuint32_t CCS:1;                 /* Classic Checksum */
      vuint32_t  :2;
      vuint32_t ID:6;                  /* Identifier */
    } B;
  } IFCR[16];

  union {                              /* Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TDFBM:1;
      vuint32_t RDFBM:1;
      vuint32_t TDLIS:1;
      vuint32_t RDLIS:1;
      vuint32_t STOP:1;
      vuint32_t SR:1;
    } B;
  } GCR;

  union {                              /* UART Preset Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t PTO:12;
    } B;
  } UARTPTO;

  union {                              /* UART Current Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t CTO:12;
    } B;
  } UARTCTO;

  union {                              /* DMA Tx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DTE:16;
    } B;
  } DMATXE;

  union {                              /* DMA Rx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DRE:16;
    } B;
  } DMARXE;

  union {                              /* PSI5-S Tx Delay register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t IFD:5;
      vuint32_t EN:1;
    } B;
  } PTD;
};


/* ============================================================================
   =============================== Module: MC_CGM =============================
   ============================================================================ */

struct MC_CGM_tag {
  uint8_t MC_CGM_reserved0[1664];
  union {                              /* Auxiliary Clock 5 Cascaded Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC0;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC1;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC2;

  uint8_t MC_CGM_reserved1[4];
  union {                              /* Auxiliary Clock 5 Cascaded Divider 10 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC10;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 11 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC11;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 12 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC12;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 13 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC13;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 20 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC20;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 21 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC21;

  union {                              /* Auxiliary Clock 5 Cascaded Divider 22 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_CDC22;

  uint8_t MC_CGM_reserved2[84];
  union {                              /* PCS Switch Duration Register */
    vuint8_t R;
    struct {
      vuint8_t SDUR:8;
    } B;
  } PCS_SDUR;

  uint8_t MC_CGM_reserved3[3];
  union {                              /* PCS Divider Change Register 1 */
    vuint32_t R;
    struct {
      vuint32_t INIT:16;
      vuint32_t  :8;
      vuint32_t RATE:8;
    } B;
  } PCS_DIVC1;

  union {                              /* PCS Divider End Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVE:20;
    } B;
  } PCS_DIVE1;

  union {                              /* PCS Divider Start Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVS:20;
    } B;
  } PCS_DIVS1;

  union {                              /* PCS Divider Change Register 2 */
    vuint32_t R;
    struct {
      vuint32_t INIT:16;
      vuint32_t  :8;
      vuint32_t RATE:8;
    } B;
  } PCS_DIVC2;

  union {                              /* PCS Divider End Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVE:20;
    } B;
  } PCS_DIVE2;

  union {                              /* PCS Divider Start Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVS:20;
    } B;
  } PCS_DIVS2;

  uint8_t MC_CGM_reserved4[12];
  union {                              /* PCS Divider Change Register 4 */
    vuint32_t R;
    struct {
      vuint32_t INIT:16;
      vuint32_t  :8;
      vuint32_t RATE:8;
    } B;
  } PCS_DIVC4;

  union {                              /* PCS Divider End Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVE:20;
    } B;
  } PCS_DIVE4;

  union {                              /* PCS Divider Start Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIVS:20;
    } B;
  } PCS_DIVS4;

  uint8_t MC_CGM_reserved5[156];
  union {                              /* System Clock Divider Ratio Change Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t SYS_DIV_RATIO_CHNG:1;
    } B;
  } SC_DIV_RC;

  union {                              /* Divider Update Type Register */
    vuint32_t R;
    struct {
      vuint32_t SYS_UPD_TYPE:1;
      vuint32_t  :31;
    } B;
  } DIV_UPD_TYPE;

  union {                              /* Divider Update Trigger Register */
    vuint32_t R;
    struct {
      vuint32_t DIV_UPD_TRIGGER:32;
    } B;
  } DIV_UPD_TRIG;

  union {                              /* Divider Update Status Register */
    vuint32_t R;
    struct {
      vuint32_t SYS_UPD_STAT:1;
      vuint32_t  :31;
    } B;
  } DIV_UPD_STAT;

  uint8_t MC_CGM_reserved6[4];
  union {                              /* System Clock Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :4;
      vuint32_t SWTRG:3;
      vuint32_t SWIP:1;
      vuint32_t  :16;
    } B;
  } SC_SS;

  union {                              /* System Clock Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC0;

  union {                              /* System Clock Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC1;

  union {                              /* System Clock Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC2;

  union {                              /* System Clock Divider 3 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC3;

  union {                              /* System Clock Divider 4 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } SC_DC4;

  uint8_t MC_CGM_reserved7[4];
  union {                              /* Auxiliary Clock 0 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC0_SC;

  union {                              /* Auxiliary Clock 0 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC0_SS;

  union {                              /* Auxiliary Clock 0 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :11;
      vuint32_t DIV:4;
      vuint32_t  :16;
    } B;
  } AC0_DC0;

  union {                              /* Auxiliary Clock 0 Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :8;
      vuint32_t DIV:7;
      vuint32_t  :16;
    } B;
  } AC0_DC1;

  union {                              /* Auxiliary Clock 0 Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :8;
      vuint32_t DIV:7;
      vuint32_t  :16;
    } B;
  } AC0_DC2;

  union {                              /* Auxiliary Clock 0 Divider 3 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :6;
      vuint32_t DIV:9;
      vuint32_t  :14;
      vuint32_t DIV_FMT:2;
    } B;
  } AC0_DC3;

  union {                              /* Auxiliary Clock 0 Divider 4 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :11;
      vuint32_t DIV:4;
      vuint32_t  :16;
    } B;
  } AC0_DC4;

  uint8_t MC_CGM_reserved8[4];
  union {                              /* Auxiliary Clock 1 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC1_SC;

  union {                              /* Auxiliary Clock 1 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC1_SS;

  union {                              /* Auxiliary Clock 1 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :8;
      vuint32_t DIV:7;
      vuint32_t  :16;
    } B;
  } AC1_DC0;

  uint8_t MC_CGM_reserved9[28];
  union {                              /* Auxiliary Clock 2 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC2_DC0;

  union {                              /* Auxiliary Clock 2 Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC2_DC1;

  uint8_t MC_CGM_reserved10[16];
  union {                              /* Auxiliary Clock 3 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC3_SC;

  union {                              /* Auxiliary Clock 3 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC3_SS;

  uint8_t MC_CGM_reserved11[24];
  union {                              /* Auxiliary Clock 4 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC4_SC;

  union {                              /* Auxiliary Clock 4 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC4_SS;

  uint8_t MC_CGM_reserved12[32];
  union {                              /* Auxiliary Clock 5 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :2;
      vuint32_t DIV:13;
      vuint32_t  :14;
      vuint32_t DIV_FMT:2;
    } B;
  } AC5_DC0;

  union {                              /* Auxiliary Clock 5 Divider 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :7;
      vuint32_t DIV:8;
      vuint32_t  :16;
    } B;
  } AC5_DC1;

  union {                              /* Auxiliary Clock 5 Divider 2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :5;
      vuint32_t DIV:10;
      vuint32_t  :16;
    } B;
  } AC5_DC2;

  uint8_t MC_CGM_reserved13[12];
  union {                              /* Auxiliary Clock 6 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC6_SC;

  union {                              /* Auxiliary Clock 6 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC6_SS;

  union {                              /* Auxiliary Clock 6 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :6;
      vuint32_t DIV:9;
      vuint32_t  :16;
    } B;
  } AC6_DC0;

  uint8_t MC_CGM_reserved14[20];
  union {                              /* Auxiliary Clock 7 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC7_SC;

  union {                              /* Auxiliary Clock 7 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC7_SS;

  union {                              /* Auxiliary Clock 7 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :6;
      vuint32_t DIV:9;
      vuint32_t  :16;
    } B;
  } AC7_DC0;

  uint8_t MC_CGM_reserved15[20];
  union {                              /* Auxiliary Clock 8 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC8_SC;

  union {                              /* Auxiliary Clock 8 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC8_SS;

  union {                              /* Auxiliary Clock 8 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC8_DC0;

  uint8_t MC_CGM_reserved16[20];
  union {                              /* Auxiliary Clock 9 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC9_SC;

  union {                              /* Auxiliary Clock 9 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC9_SS;

  union {                              /* Auxiliary Clock 9 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :9;
      vuint32_t DIV:6;
      vuint32_t  :16;
    } B;
  } AC9_DC0;

  uint8_t MC_CGM_reserved17[20];
  union {                              /* Auxiliary Clock 10 Select Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELCTL:4;
      vuint32_t  :24;
    } B;
  } AC10_SC;

  union {                              /* Auxiliary Clock 10 Select Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t SELSTAT:4;
      vuint32_t  :24;
    } B;
  } AC10_SS;

  union {                              /* Auxiliary Clock 10 Divider 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t DE:1;
      vuint32_t  :11;
      vuint32_t DIV:4;
      vuint32_t  :16;
    } B;
  } AC10_DC0;
};


/* ============================================================================
   =============================== Module: MC_ME ==============================
   ============================================================================ */

struct MC_ME_tag {
  union {                              /* Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t S_CURRENTMODE:4;
      vuint32_t S_MTRANS:1;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t S_PDO:1;
      vuint32_t  :2;
      vuint32_t S_MVR:1;
      vuint32_t  :2;
      vuint32_t S_FLA:2;
      vuint32_t  :8;
      vuint32_t S_PLL1:1;
      vuint32_t S_PLL0:1;
      vuint32_t S_XOSC:1;
      vuint32_t S_IRC:1;
      vuint32_t S_SYSCLK:4;
    } B;
  } GS;

  union {                              /* Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t TARGET_MODE:4;
      vuint32_t  :12;
      vuint32_t KEY:16;
    } B;
  } MCTL;

  union {                              /* Mode Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RESET_DEST:1;
      vuint32_t  :4;
      vuint32_t STOP0:1;
      vuint32_t  :1;
      vuint32_t HALT0:1;
      vuint32_t RUN3:1;
      vuint32_t RUN2:1;
      vuint32_t RUN1:1;
      vuint32_t RUN0:1;
      vuint32_t DRUN:1;
      vuint32_t SAFE:1;
      vuint32_t TEST:1;
      vuint32_t RESET_FUNC:1;
    } B;
  } ME;

  union {                              /* Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t I_ICONF_CC:1;
      vuint32_t I_ICONF_CU:1;
      vuint32_t I_ICONF:1;
      vuint32_t I_IMODE:1;
      vuint32_t I_SAFE:1;
      vuint32_t I_MTC:1;
    } B;
  } IS;

  union {                              /* Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t M_ICONF_CC:1;
      vuint32_t M_ICONF_CU:1;
      vuint32_t M_ICONF:1;
      vuint32_t M_IMODE:1;
      vuint32_t M_SAFE:1;
      vuint32_t M_MTC:1;
    } B;
  } IM;

  union {                              /* Invalid Mode Transition Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t S_MRIG:1;
      vuint32_t S_MTI:1;
      vuint32_t S_MRI:1;
      vuint32_t S_DMA:1;
      vuint32_t S_NMA:1;
      vuint32_t S_SEA:1;
    } B;
  } IMTS;

  union {                              /* Debug Mode Transition Status Register */
    vuint32_t R;
    struct {
      vuint32_t PREVIOUS_MODE:4;
      vuint32_t  :4;
      vuint32_t MPH_BUSY:1;
      vuint32_t  :2;
      vuint32_t PMC_PROG:1;
      vuint32_t DBG_MODE:1;
      vuint32_t CCKL_PROG:1;
      vuint32_t PCS_PROG:1;
      vuint32_t SMR:1;
      vuint32_t  :1;
      vuint32_t VREG_CSRC_SC:1;
      vuint32_t CSRC_CSRC_SC:1;
      vuint32_t IRC_SC:1;
      vuint32_t SCSRC_SC:1;
      vuint32_t SYSCLK_SW:1;
      vuint32_t  :1;
      vuint32_t FLASH_SC:1;
      vuint32_t CDP_PRPH_224_255:1;
      vuint32_t CDP_PRPH_192_223:1;
      vuint32_t CDP_PRPH_160_191:1;
      vuint32_t CDP_PRPH_128_159:1;
      vuint32_t CDP_PRPH_96_127:1;
      vuint32_t CDP_PRPH_64_95:1;
      vuint32_t CDP_PRPH_32_63:1;
      vuint32_t CDP_PRPH_0_31:1;
    } B;
  } DMTS;

  uint8_t MC_ME_reserved0[4];
  union {                              /* RESET Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } RESET_MC;

  union {                              /* TEST Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } TEST_MC;

  union {                              /* SAFE Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } SAFE_MC;

  union {                              /* DRUN Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } DRUN_MC;

  union {                              /* RUN0 Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } RUN_MC[4];

  union {                              /* HALT0 Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } HALT0_MC;

  uint8_t MC_ME_reserved1[4];
  union {                              /* STOP0 Mode Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PWRLVL:3;
      vuint32_t  :4;
      vuint32_t PDO:1;
      vuint32_t  :2;
      vuint32_t MVRON:1;
      vuint32_t  :2;
      vuint32_t FLAON:2;
      vuint32_t  :8;
      vuint32_t PLL1ON:1;
      vuint32_t PLL0ON:1;
      vuint32_t XOSCON:1;
      vuint32_t IRCON:1;
      vuint32_t SYSCLK:4;
    } B;
  } STOP0_MC;

  uint8_t MC_ME_reserved2[20];
  union {                              /* Peripheral Status Register 0 */
    vuint32_t R;
    struct {
      vuint32_t S_PIT_RTC_1:1;
      vuint32_t S_PIT_RTC_0:1;
      vuint32_t  :14;
      vuint32_t S_SIUL:1;
      vuint32_t  :3;
      vuint32_t S_SIPI_0:1;
      vuint32_t  :1;
      vuint32_t S_LFAST_0:1;
      vuint32_t  :5;
      vuint32_t S_EBI_0:1;
      vuint32_t  :3;
    } B;
  } PS0;

  union {                              /* Peripheral Status Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t S_ADCSD_0:1;
      vuint32_t S_ADCSD_2:1;
      vuint32_t S_ADCSD_4:1;
      vuint32_t S_ADCSD_6:1;
      vuint32_t S_ADCSD_8:1;
      vuint32_t  :17;
      vuint32_t S_CRC_0:1;
      vuint32_t  :1;
      vuint32_t S_DMAMUX_0:1;
      vuint32_t  :4;
    } B;
  } PS1;

  union {                              /* Peripheral Status Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t S_DSPI_12:1;
      vuint32_t S_LINFlexD_0:1;
      vuint32_t S_LINFlexD_1:1;
      vuint32_t  :5;
      vuint32_t S_LINFlexD_14:1;
      vuint32_t S_LINFlexD_16:1;
      vuint32_t  :9;
      vuint32_t S_CAN_RAM_CTRL:1;
      vuint32_t  :1;
      vuint32_t S_TTCAN:1;
      vuint32_t  :1;
      vuint32_t S_MCAN_1:1;
      vuint32_t S_MCAN_2:1;
      vuint32_t S_MCAN_3:1;
      vuint32_t S_MCAN_4:1;
      vuint32_t  :3;
    } B;
  } PS2;

  union {                              /* Peripheral Status Register 3 */
    vuint32_t R;
    struct {
      vuint32_t S_ADCSAR_0:1;
      vuint32_t  :3;
      vuint32_t S_ADCSAR_4:1;
      vuint32_t  :10;
      vuint32_t S_ADCSAR_b:1;
      vuint32_t S_PSI5_0:1;
      vuint32_t  :3;
      vuint32_t S_FLEXRAY_0:1;
      vuint32_t  :2;
      vuint32_t S_SENT_0:1;
      vuint32_t  :2;
      vuint32_t S_IIC_0:1;
      vuint32_t  :1;
      vuint32_t S_DSPI_0:1;
      vuint32_t S_DSPI_1:1;
      vuint32_t S_DSPI_4:1;
      vuint32_t S_DSPI_6:1;
    } B;
  } PS3;

  union {                              /* Peripheral Status Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t S_GTMINT:1;
    } B;
  } PS4;

  union {                              /* Peripheral Status Register 5 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t S_ADCSD_1:1;
      vuint32_t S_ADCSD_3:1;
      vuint32_t S_ADCSD_5:1;
      vuint32_t S_ADCSD_7:1;
      vuint32_t S_ADCSD_9:1;
      vuint32_t  :17;
      vuint32_t S_CRC_1:1;
      vuint32_t  :3;
      vuint32_t S_PSI5S_0:1;
      vuint32_t  :2;
    } B;
  } PS5;

  union {                              /* Peripheral Status Register 6 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t S_LINFlexD_2:1;
      vuint32_t  :6;
      vuint32_t S_LINFlexD_15:1;
      vuint32_t  :21;
    } B;
  } PS6;

  union {                              /* Peripheral Status Register 7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t S_ADCSAR_1:1;
      vuint32_t S_ADCSAR_2:1;
      vuint32_t S_ADCSAR_3:1;
      vuint32_t  :1;
      vuint32_t S_ADCSAR_5:1;
      vuint32_t S_ADCSAR_6:1;
      vuint32_t S_ADCSAR_7:1;
      vuint32_t S_ADCSAR_8:1;
      vuint32_t S_ADCSAR_9:1;
      vuint32_t S_ADCSAR_10:1;
      vuint32_t  :5;
      vuint32_t S_PSI5_1:1;
      vuint32_t  :3;
      vuint32_t S_FLEXRAY_1:1;
      vuint32_t  :2;
      vuint32_t S_SENT_1:1;
      vuint32_t  :2;
      vuint32_t S_IIC_1:1;
      vuint32_t  :1;
      vuint32_t S_DSPI_2:1;
      vuint32_t S_DSPI_3:1;
      vuint32_t S_DSPI_5:1;
      vuint32_t  :1;
    } B;
  } PS7;

  union {                              /* Run Peripheral Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RUN3:1;
      vuint32_t RUN2:1;
      vuint32_t RUN1:1;
      vuint32_t RUN0:1;
      vuint32_t DRUN:1;
      vuint32_t SAFE:1;
      vuint32_t TEST:1;
      vuint32_t RESET:1;
    } B;
  } RUN_PC[8];

  union {                              /* Low-Power Peripheral Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t STOP0:1;
      vuint32_t  :1;
      vuint32_t HALT0:1;
      vuint32_t  :8;
    } B;
  } LP_PC[8];

  uint8_t MC_ME_reserved3[3];
  union {                              /* EBI_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL3;

  uint8_t MC_ME_reserved4[5];
  union {                              /* LFAST_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL9;

  uint8_t MC_ME_reserved5[1];
  union {                              /* SIPI_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL11;

  uint8_t MC_ME_reserved6[3];
  union {                              /* SIUL Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL15;

  uint8_t MC_ME_reserved7[14];
  union {                              /* PIT_RTC_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL30;

  union {                              /* PIT_RTC_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL31;

  uint8_t MC_ME_reserved8[4];
  union {                              /* DMAMUX_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL36;

  uint8_t MC_ME_reserved9[1];
  union {                              /* CRC_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL38;

  uint8_t MC_ME_reserved10[17];
  union {                              /* ADCSD_8 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL56;

  union {                              /* ADCSD_6 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL57;

  union {                              /* ADCSD_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL58;

  union {                              /* ADCSD_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL59;

  union {                              /* ADCSD_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL60;

  uint8_t MC_ME_reserved11[6];
  union {                              /* MCAN_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL67;

  union {                              /* MCAN_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL68;

  union {                              /* MCAN_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL69;

  union {                              /* MCAN_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL70;

  uint8_t MC_ME_reserved12[1];
  union {                              /* TTCAN Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL72;

  uint8_t MC_ME_reserved13[1];
  union {                              /* CAN_RAM_CTRL Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL74;

  uint8_t MC_ME_reserved14[9];
  union {                              /* LINFlexD_16 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL84;

  union {                              /* LINFlexD_14 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL85;

  uint8_t MC_ME_reserved15[5];
  union {                              /* LINFlexD_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL91;

  union {                              /* LINFlexD_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL92;

  union {                              /* DSPI_12 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL93;

  uint8_t MC_ME_reserved16[2];
  union {                              /* DSPI_6 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL96;

  union {                              /* DSPI_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL97;

  union {                              /* DSPI_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL98;

  union {                              /* DSPI_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL99;

  uint8_t MC_ME_reserved17[1];
  union {                              /* IIC_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL101;

  uint8_t MC_ME_reserved18[2];
  union {                              /* SENT_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL104;

  uint8_t MC_ME_reserved19[2];
  union {                              /* FLEXRAY_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL107;

  uint8_t MC_ME_reserved20[3];
  union {                              /* PSI5_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL111;

  union {                              /* ADCSAR_b Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL112;

  uint8_t MC_ME_reserved21[10];
  union {                              /* ADCSAR_4 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL123;

  uint8_t MC_ME_reserved22[3];
  union {                              /* ADCSAR_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL127;

  union {                              /* GTMINT Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL128;

  uint8_t MC_ME_reserved23[33];
  union {                              /* PSI5_S_0 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL162;

  uint8_t MC_ME_reserved24[3];
  union {                              /* CRC_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL166;

  uint8_t MC_ME_reserved25[17];
  union {                              /* ADCSD_9 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL184;

  union {                              /* ADCSD_7 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL185;

  union {                              /* ADCSD_5 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL186;

  union {                              /* ADCSD_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL187;

  union {                              /* ADCSD_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL188;

  uint8_t MC_ME_reserved26[24];
  union {                              /* LINFlexD_15 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL213;

  uint8_t MC_ME_reserved27[6];
  union {                              /* LINFlexD_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL220;

  uint8_t MC_ME_reserved28[4];
  union {                              /* DSPI_5 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL225;

  union {                              /* DSPI_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL226;

  union {                              /* DSPI_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL227;

  uint8_t MC_ME_reserved29[1];
  union {                              /* IIC_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL229;

  uint8_t MC_ME_reserved30[2];
  union {                              /* SENT_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL232;

  uint8_t MC_ME_reserved31[2];
  union {                              /* FLEXRAY_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL235;

  uint8_t MC_ME_reserved32[3];
  union {                              /* PSI5_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL239;

  uint8_t MC_ME_reserved33[5];
  union {                              /* ADCSAR_10 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL245;

  union {                              /* ADCSAR_9 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL246;

  union {                              /* ADCSAR_8 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL247;

  union {                              /* ADCSAR_7 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL248;

  union {                              /* ADCSAR_6 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL249;

  union {                              /* ADCSAR_5 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL250;

  uint8_t MC_ME_reserved34[1];
  union {                              /* ADCSAR_3 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL252;

  union {                              /* ADCSAR_2 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL253;

  union {                              /* ADCSAR_1 Peripheral Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :1;
      vuint8_t DBG_F:1;
      vuint8_t LP_CFG:3;
      vuint8_t RUN_CFG:3;
    } B;
  } PCTL254;

  uint8_t MC_ME_reserved35[1];
  union {                              /* Core Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t S_CORE4:1;
      vuint32_t S_CORE3:1;
      vuint32_t S_CORE2:1;
      vuint32_t S_CORE1:1;
      vuint32_t S_CORE0:1;
    } B;
  } CS;

  union {                              /* CORE0 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL0;

  union {                              /* CORE1 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL1;

  union {                              /* CORE2 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL2;

  union {                              /* CORE3 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL3;

  union {                              /* CORE4 Core Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :5;
      vuint16_t STOP0:1;
      vuint16_t  :1;
      vuint16_t HALT0:1;
      vuint16_t RUN3:1;
      vuint16_t RUN2:1;
      vuint16_t RUN1:1;
      vuint16_t RUN0:1;
      vuint16_t DRUN:1;
      vuint16_t SAFE:1;
      vuint16_t TEST:1;
      vuint16_t RESET:1;
    } B;
  } CCTL4;

  uint8_t MC_ME_reserved36[18];
  union {                              /* CORE0 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR0;

  union {                              /* CORE1 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR1;

/* >>>> v1.0_issue (MC_ME):  expected CUT1 supports CADDR2, CUT2 does not <<<<<
  Add #define CUT1 to header file
*/  
#ifdef CUT1
  union {                              /* CORE2 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR2;
#else
  uint8_t MC_ME_reserved37[4];
#endif
  union {                              /* CORE3 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR3;

  union {                              /* CORE4 Core Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:30;
      vuint32_t  :1;
      vuint32_t RMC:1;
    } B;
  } CADDR4;
};


/* ============================================================================
   =============================== Module: MC_PCU =============================
   ============================================================================ */

struct MC_PCU_tag {
  uint8_t MC_PCU_reserved0[64];
  union {                              /* Power Domain Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t PD0:1;
    } B;
  } PSTAT;
};


/* ============================================================================
   =============================== Module: MC_RGM =============================
   ============================================================================ */

struct MC_RGM_tag {
  union {                              /* 'Destructive' Event Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t F_VOR_DEST:1;
      vuint32_t F_TSR_DEST:1;
      vuint32_t  :7;
      vuint32_t F_HSM_DEST:1;
      vuint32_t F_SSCM_DEST:1;
      vuint32_t  :3;
      vuint32_t F_JTAG_DEST:1;
      vuint32_t F_FIF:1;
      vuint32_t F_EDR:1;
      vuint32_t  :2;
      vuint32_t F_SUF:1;
      vuint32_t F_FFRR:1;
      vuint32_t F_SOFT_DEST:1;
      vuint32_t  :1;
      vuint32_t F_PORST:1;
      vuint32_t F_POR:1;
    } B;
  } DES;

  uint8_t MC_RGM_reserved0[12];
  union {                              /* 'Destructive' Event Reset Disable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t D_VOR_DEST:1;
      vuint32_t  :8;
      vuint32_t D_HSM_DEST:1;
      vuint32_t D_SSCM_DEST:1;
      vuint32_t  :3;
      vuint32_t D_JTAG_DEST:1;
      vuint32_t D_FIF:1;
      vuint32_t D_EDR:1;
      vuint32_t  :2;
      vuint32_t D_SUF:1;
      vuint32_t D_FFRR:1;
      vuint32_t D_SOFT_DEST:1;
      vuint32_t  :1;
      vuint32_t D_PORST:1;
      vuint32_t D_POR:1;
    } B;
  } DERD;

  uint8_t MC_RGM_reserved1[12];
  union {                              /* 'Destructive' Event Alternate Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t AR_PORST:1;
      vuint32_t  :1;
    } B;
  } DEAR;

  uint8_t MC_RGM_reserved2[12];
  union {                              /* 'Destructive' Bidirectional Reset Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t BE_VOR_DEST:1;
      vuint32_t BE_TSR_DEST:1;
      vuint32_t  :7;
      vuint32_t BE_HSM_DEST:1;
      vuint32_t BE_SSCM_DEST:1;
      vuint32_t  :3;
      vuint32_t BE_JTAG_DEST:1;
      vuint32_t BE_FIF:1;
      vuint32_t BE_EDR:1;
      vuint32_t  :2;
      vuint32_t BE_SUF:1;
      vuint32_t BE_FFRR:1;
      vuint32_t BE_SOFT_DEST:1;
      vuint32_t  :1;
      vuint32_t BE_PORST:1;
      vuint32_t BE_POR:1;
    } B;
  } DBRE;

  uint8_t MC_RGM_reserved3[716];
  union {                              /* 'Functional' Event Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t F_VOR_FUNC:1;
      vuint32_t F_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t F_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t F_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t F_FCCU_SOFT:1;
      vuint32_t F_FCCU_HARD:1;
      vuint32_t  :1;
      vuint32_t F_SOFT_FUNC:1;
      vuint32_t F_ST_DONE:1;
      vuint32_t F_ESR1:1;
      vuint32_t F_ESR0:1;
    } B;
  } FES;

  uint8_t MC_RGM_reserved4[12];
  union {                              /* 'Functional' Event Reset Disable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t D_VOR_FUNC:1;
      vuint32_t D_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t D_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t D_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t D_FCCU_SOFT:1;
      vuint32_t D_FCCU_HARD:1;
      vuint32_t  :2;
      vuint32_t D_ST_DONE:1;
      vuint32_t D_ESR1:1;
      vuint32_t D_ESR0:1;
    } B;
  } FERD;

  uint8_t MC_RGM_reserved5[12];
  union {                              /* 'Functional' Event Alternate Request Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t AR_VOR_FUNC:1;
      vuint32_t AR_TSR_FUNC:1;
      vuint32_t  :21;
      vuint32_t AR_ESR1:1;
      vuint32_t  :1;
    } B;
  } FEAR;

  uint8_t MC_RGM_reserved6[12];
  union {                              /* 'Functional' Bidirectional Reset Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t BE_VOR_FUNC:1;
      vuint32_t BE_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t BE_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t BE_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t BE_FCCU_SOFT:1;
      vuint32_t BE_FCCU_HARD:1;
      vuint32_t  :1;
      vuint32_t BE_SOFT_FUNC:1;
      vuint32_t BE_ST_DONE:1;
      vuint32_t BE_ESR1:1;
      vuint32_t BE_ESR0:1;
    } B;
  } FBRE;

  uint8_t MC_RGM_reserved7[12];
  union {                              /* 'Functional' Event Short Sequence Register */
    vuint32_t R;
    struct {
      vuint32_t  :7;
      vuint32_t SS_VOR_FUNC:1;
      vuint32_t SS_TSR_FUNC:1;
      vuint32_t  :7;
      vuint32_t SS_HSM_FUNC:1;
      vuint32_t  :4;
      vuint32_t SS_JTAG_FUNC:1;
      vuint32_t  :3;
      vuint32_t SS_FCCU_SOFT:1;
      vuint32_t SS_FCCU_HARD:1;
      vuint32_t  :1;
      vuint32_t SS_SOFT_FUNC:1;
      vuint32_t SS_ST_DONE:1;
      vuint32_t SS_ESR1:1;
      vuint32_t SS_ESR0:1;
    } B;
  } FESS;

  uint8_t MC_RGM_reserved8[704];
  union {                              /* 'Functional' Reset Escalation Threshold Register */
    vuint8_t R;
    struct {
      vuint8_t  :4;
      vuint8_t FRET:4;
    } B;
  } FRET;

  uint8_t MC_RGM_reserved9[3];
  union {                              /* 'Destructive' Reset Escalation Threshold Register */
    vuint8_t R;
    struct {
      vuint8_t  :4;
      vuint8_t DRET:4;
    } B;
  } DRET;

  uint8_t MC_RGM_reserved10[3];
  union {                              /* External Reset Output Extension Control Register */
    vuint8_t R;
    struct {
      vuint8_t  :6;
      vuint8_t ERIS:1;
      vuint8_t EROEC:1;
    } B;
  } EROEC;

  uint8_t MC_RGM_reserved11[3];
  union {                              /* Peripheral Reset Register 0 */
    vuint32_t R;
    struct {
      vuint32_t PIT_RTC_1_RST:1;
      vuint32_t PIT_RTC_0_RST:1;
      vuint32_t  :14;
      vuint32_t SIUL_RST:1;
      vuint32_t  :3;
      vuint32_t SIPI_0_RST:1;
      vuint32_t  :1;
      vuint32_t LFAST_0_RST:1;
      vuint32_t  :5;
      vuint32_t EBI_0_RST:1;
      vuint32_t  :3;
    } B;
  } PRST0;

  union {                              /* Peripheral Reset Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ADCSD_0_RST:1;
      vuint32_t ADCSD_2_RST:1;
      vuint32_t ADCSD_4_RST:1;
      vuint32_t ADCSD_6_RST:1;
      vuint32_t ADCSD_8_RST:1;
      vuint32_t  :17;
      vuint32_t CRC_0_RST:1;
      vuint32_t  :1;
      vuint32_t DMAMUX_0_RST:1;
      vuint32_t  :4;
    } B;
  } PRST1;

  union {                              /* Peripheral Reset Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t DSPI_12_RST:1;
      vuint32_t LINFlexD_0_RST:1;
      vuint32_t LINFlexD_1_RST:1;
      vuint32_t  :5;
      vuint32_t LINFlexD_14_RST:1;
      vuint32_t LINFlexD_16_RST:1;
      vuint32_t  :9;
      vuint32_t CAN_RAM_CTR_RST:1;
      vuint32_t  :1;
      vuint32_t TTCAN_RST:1;
      vuint32_t  :1;
      vuint32_t MCAN_1_RST:1;
      vuint32_t MCAN_2_RST:1;
      vuint32_t MCAN_3_RST:1;
      vuint32_t MCAN_4_RST:1;
      vuint32_t  :3;
    } B;
  } PRST2;

  union {                              /* Peripheral Reset Register 3 */
    vuint32_t R;
    struct {
      vuint32_t ADCSAR_0_RST:1;
      vuint32_t  :3;
      vuint32_t ADCSAR_4_RST:1;
      vuint32_t  :10;
      vuint32_t ADCSAR_b_RST:1;
      vuint32_t PSI5_0_RST:1;
      vuint32_t  :3;
      vuint32_t FLEXRAY_0_RST:1;
      vuint32_t  :2;
      vuint32_t SENT_0_RST:1;
      vuint32_t  :2;
      vuint32_t IIC_0_RST:1;
      vuint32_t  :1;
      vuint32_t DSPI_0_RST:1;
      vuint32_t DSPI_1_RST:1;
      vuint32_t DSPI_4_RST:1;
      vuint32_t DSPI_6_RST:1;
    } B;
  } PRST3;

  union {                              /* Peripheral Reset Register 4 */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t GTMINT_RST:1;
    } B;
  } PRST4;

  union {                              /* Peripheral Reset Register 5 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t ADCSD_1_RST:1;
      vuint32_t ADCSD_3_RST:1;
      vuint32_t ADCSD_5_RST:1;
      vuint32_t ADCSD_7_RST:1;
      vuint32_t ADCSD_9_RST:1;
      vuint32_t  :14;
      vuint32_t FCCU_RST:1;
      vuint32_t  :2;
      vuint32_t CRC_1_RST:1;
      vuint32_t  :3;
      vuint32_t PSI5_S_0_RST:1;
      vuint32_t  :2;
    } B;
  } PRST5;

  union {                              /* Peripheral Reset Register 6 */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t LINFlexD_2_RST:1;
      vuint32_t  :6;
      vuint32_t LINFlexD_15_RST:1;
      vuint32_t  :21;
    } B;
  } PRST6;

  union {                              /* Peripheral Reset Register 7 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t ADCSAR_1_RST:1;
      vuint32_t ADCSAR_2_RST:1;
      vuint32_t ADCSAR_3_RST:1;
      vuint32_t  :1;
      vuint32_t ADCSAR_5_RST:1;
      vuint32_t ADCSAR_6_RST:1;
      vuint32_t ADCSAR_7_RST:1;
      vuint32_t ADCSAR_8_RST:1;
      vuint32_t ADCSAR_9_RST:1;
      vuint32_t ADCSAR_10_RST:1;
      vuint32_t  :5;
      vuint32_t PSI5_1_RST:1;
      vuint32_t  :3;
      vuint32_t FLEXRAY_1_RST:1;
      vuint32_t  :2;
      vuint32_t SENT_1_RST:1;
      vuint32_t  :2;
      vuint32_t IIC_1_RST:1;
      vuint32_t  :1;
      vuint32_t DSPI_2_RST:1;
      vuint32_t DSPI_3_RST:1;
      vuint32_t DSPI_5_RST:1;
      vuint32_t  :1;
    } B;
  } PRST7;
};


/* ============================================================================
   =============================== Module: MEMU ===============================
   ============================================================================ */

struct MEMU_tag {
  union {                              /* Control register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SWR:1;
      vuint32_t  :15;
    } B;
  } CTRL;

  union {                              /* Error flag register */
    vuint32_t R;
    struct {
      vuint32_t  :11;
      vuint32_t PR_CE:1;
      vuint32_t PR_UCE:1;
      vuint32_t PR_CEO:1;
      vuint32_t PR_UCO:1;
      vuint32_t PR_EBO:1;
      vuint32_t  :3;
      vuint32_t F_CE:1;
      vuint32_t F_UCE:1;
      vuint32_t F_CEO:1;
      vuint32_t F_UCO:1;
      vuint32_t F_EBO:1;
      vuint32_t  :3;
      vuint32_t SR_CE:1;
      vuint32_t SR_UCE:1;
      vuint32_t SR_CEO:1;
      vuint32_t SR_UCO:1;
      vuint32_t SR_EBO:1;
    } B;
  } ERR_FLAG;

  uint8_t MEMU_reserved0[4];
  union {                              /* Debug register */
    vuint32_t R;
    struct {
      vuint32_t  :11;
      vuint32_t FR_PR_CE:1;
      vuint32_t FR_PR_UCE:1;
      vuint32_t FR_PR_CEO:1;
      vuint32_t FR_PR_UCO:1;
      vuint32_t FR_PR_EBO:1;
      vuint32_t  :3;
      vuint32_t FR_F_CE:1;
      vuint32_t FR_F_UCE:1;
      vuint32_t FR_F_CEO:1;
      vuint32_t FR_F_UCO:1;
      vuint32_t FR_F_EBO:1;
      vuint32_t  :3;
      vuint32_t FR_SR_CE:1;
      vuint32_t FR_SR_UCE:1;
      vuint32_t FR_SR_CEO:1;
      vuint32_t FR_SR_UCO:1;
      vuint32_t FR_SR_EBO:1;
    } B;
  } DEBUG;

  uint8_t MEMU_reserved1[16];
  struct {
    union {                            /* System RAM correctable error reporting table status register */
      vuint32_t R;
      struct {
        vuint32_t VLD:1;
        vuint32_t  :23;
        vuint32_t BAD_BIT:8;
      } B;
    } STS;
    union {                            /* System RAM correctable error reporting table address register */
      vuint32_t R;
      struct {
        vuint32_t ERR_ADD:32;
      } B;
    } ADDR;
  } SYS_RAM_CERR[10];

  union {                              /* System RAM uncorrectable error reporting table status register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :31;
    } B;
  } SYS_RAM_UNCERR_STS;

  union {                              /* System RAM uncorrectable error reporting table address register */
    vuint32_t R;
    struct {
      vuint32_t ERR_ADD:32;
    } B;
  } SYS_RAM_UNCERR_ADDR;

  union {                              /* System RAM concurrent overflow register */
    vuint32_t R;
    struct {
      vuint32_t OFLW:32;
    } B;
  } SYS_RAM_OFLW[3];

  uint8_t MEMU_reserved2[1436];
  struct {
    union {                            /* Peripheral RAM correctable error reporting table status register */
      vuint32_t R;
      struct {
        vuint32_t VLD:1;
        vuint32_t  :23;
        vuint32_t BAD_BIT:8;
      } B;
    } STS;
    union {                            /* Peripheral RAM correctable error reporting table address register */
      vuint32_t R;
      struct {
        vuint32_t ERR_ADD:32;
      } B;
    } ADDR;
  } PERIPH_RAM_CERR[2];

  union {                              /* Peripheral RAM uncorrectable error reporting table status register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :31;
    } B;
  } PERIPH_RAM_UNCERR_STS;

  union {                              /* Peripheral RAM uncorrectable error reporting table address register */
    vuint32_t R;
    struct {
      vuint32_t ERR_ADD:32;
    } B;
  } PERIPH_RAM_UNCERR_ADDR;

  union {                              /* Peripheral RAM concurrent overflow register */
    vuint32_t R;
    struct {
      vuint32_t OFLW:32;
    } B;
  } PERIPH_RAM_OFLW0;

  uint8_t MEMU_reserved3[1508];
  struct {
    union {                            /* Flash memory correctable error reporting table status register */
      vuint32_t R;
      struct {
        vuint32_t VLD:1;
        vuint32_t  :23;
        vuint32_t BAD_BIT:8;
      } B;
    } STS;
    union {                            /* Flash memory correctable error reporting table address register */
      vuint32_t R;
      struct {
        vuint32_t ERR_ADD:32;
      } B;
    } ADDR;
  } FLASH_CERR[20];

  union {                              /* Flash memory uncorrectable error reporting table status register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :31;
    } B;
  } FLASH_UNCERR_STS;

  union {                              /* Flash memory uncorrectable error reporting table address register */
    vuint32_t R;
    struct {
      vuint32_t ERR_ADD:32;
    } B;
  } FLASH_UNCERR_ADDR;

  union {                              /* Flash memory concurrent overflow register */
    vuint32_t R;
    struct {
      vuint32_t OFLW:32;
    } B;
  } FLASH_OFLW0;
};


/* ============================================================================
   =============================== Module: M_CAN ==============================
   ============================================================================ */

struct M_CAN_tag {
  union {                              /* Core Release Register */
    vuint32_t R;
    struct {
      vuint32_t REL:4;
      vuint32_t STEP:4;
      vuint32_t SUBSTEP:4;
      vuint32_t YEAR:4;
      vuint32_t MON:8;
      vuint32_t DAY:8;
    } B;
  } CREL;

  union {                              /* Endian Register */
    vuint32_t R;
    struct {
      vuint32_t ETV:32;
    } B;
  } ENDN;

  uint8_t M_CAN_reserved0[4];
  union {                              /* Fast Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t TDCO:5;                /* Transceiver Delay Compensation Offset */
      vuint32_t TDC:1;                 /* Transceiver Delay Compensation */
      vuint32_t  :2;
      vuint32_t FBRP:5;                /* Fast Baud Rate Prescaler */
      vuint32_t  :4;
      vuint32_t FTSEG1:4;              /* Fast time segment before sample point */
      vuint32_t  :1;
      vuint32_t FTSEG2:3;              /* Fast time segment before sample point */
      vuint32_t  :2;
      vuint32_t FSJW:2;                /* Fast (Re) Synchronization Jump Width */
    } B;
  } FBTP;

  union {                              /* Test Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t TDCV:6;                /* Transceiver Delay Compensation Value */
      vuint32_t RX:1;
      vuint32_t TX:2;
      vuint32_t LBCK:1;
      vuint32_t  :4;
    } B;
  } TEST;

  union {                              /* RAM Watchdog Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t WDV:8;
      vuint32_t WDC:8;
    } B;
  } RWD;

  union {                              /* CC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :1;
      vuint32_t TXP:1;                 /* Transmit Pause */
      vuint32_t FDBS:1;                /* CAN FD Bit Rate Switching */
      vuint32_t FDO:1;                 /* Fast Frame Mode Active */
      vuint32_t CMR:2;                 /* CAN Mode Request */
      vuint32_t CME:2;                 /* CAN Mode Enable */
      vuint32_t TEST:1;
      vuint32_t DAR:1;
      vuint32_t MON:1;
      vuint32_t CSR:1;
      vuint32_t CSA:1;
      vuint32_t ASM:1;
      vuint32_t CCE:1;
      vuint32_t INIT:1;
    } B;
  } CCCR;

  union {                              /* Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t BRP:10;                /* Baud Rate Prescaler */
      vuint32_t  :2;
      vuint32_t TSEG1:6;
      vuint32_t TSEG2:4;
      vuint32_t SJW:4;
    } B;
  } BTP;

  union {                              /* Timestamp Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t TCP:4;
      vuint32_t  :14;
      vuint32_t TSS:2;
    } B;
  } TSCC;

  union {                              /* Timestamp Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TSC:16;                /* Timestamp Counter */
    } B;
  } TSCV;

  union {                              /* Timeout Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t TOP:16;
      vuint32_t  :13;
      vuint32_t TOS:2;
      vuint32_t ETOC:1;
    } B;
  } TOCC;

  union {                              /* Timeout Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TOC:16;
    } B;
  } TOCV;

  uint8_t M_CAN_reserved1[16];
  union {                              /* Error Counter Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CEL:8;
      vuint32_t RP:1;
      vuint32_t REC:7;
      vuint32_t TEC:8;
    } B;
  } ECR;

  union {                              /* Protocol Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t REDL:1;                /* Received CAN FD Message with EDL flag */
      vuint32_t RBRS:1;                /* BRS flag of last received CAN FD Message */
      vuint32_t RESI:1;                /* ESI CAN FD Message with ESI flag */
      vuint32_t FLEC:3;                /* Fast Last Error Code */
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ACT:2;
      vuint32_t LEC:3;
    } B;
  } PSR;

  uint8_t M_CAN_reserved2[8];
  union {                              /* Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t STE:1;
      vuint32_t FOE:1;
      vuint32_t ACKE:1;
      vuint32_t BE:1;
      vuint32_t CRCE:1;
      vuint32_t WDI:1;
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ELO:1;
      vuint32_t BEU:1;
      vuint32_t BEC:1;
      vuint32_t DRX:1;                 /* Message stored to Dedicated Rx Buffer */
      vuint32_t TOO:1;
      vuint32_t MRAF:1;                /* Message RAM Access Failure */
      vuint32_t TSW:1;
      vuint32_t TEFL:1;
      vuint32_t TEFF:1;
      vuint32_t TEFW:1;
      vuint32_t TEFN:1;
      vuint32_t TFE:1;
      vuint32_t TCF:1;
      vuint32_t TC:1;
      vuint32_t HPM:1;
      vuint32_t RF1L:1;
      vuint32_t RF1F:1;
      vuint32_t RF1W:1;
      vuint32_t RF1N:1;
      vuint32_t RF0L:1;
      vuint32_t RF0F:1;
      vuint32_t RF0W:1;
      vuint32_t RF0N:1;
    } B;
  } IR;

  union {                              /* Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t STEE:1;
      vuint32_t FOEE:1;
      vuint32_t ACKEE:1;
      vuint32_t BEE:1;
      vuint32_t CRCEE:1;
      vuint32_t WDIE:1;
      vuint32_t BOE:1;
      vuint32_t EWE:1;
      vuint32_t EPE:1;
      vuint32_t ELOE:1;
      vuint32_t BEUE:1;
      vuint32_t BECE:1;
      vuint32_t DRXE:1;                /* Message stored to Dedicated Rx Buffer Interrupt Enable */
      vuint32_t TOOE:1;
      vuint32_t MRAFE:1;
      vuint32_t TSWE:1;
      vuint32_t TEFLE:1;
      vuint32_t TEFFE:1;
      vuint32_t TEFWE:1;
      vuint32_t TEFNE:1;
      vuint32_t TFEE:1;
      vuint32_t TCFE:1;
      vuint32_t TCE:1;
      vuint32_t HPME:1;
      vuint32_t RF1LE:1;
      vuint32_t RF1FE:1;
      vuint32_t RF1WE:1;
      vuint32_t RF1NE:1;
      vuint32_t RF0LE:1;
      vuint32_t RF0FE:1;
      vuint32_t RF0WE:1;
      vuint32_t RF0NE:1;
    } B;
  } IE;

  union {                              /* Interrupt Line Select Register */
    vuint32_t R;
    struct {
      vuint32_t STEL:1;
      vuint32_t FOEL:1;
      vuint32_t ACKEL:1;
      vuint32_t BEL:1;
      vuint32_t CRCEL:1;
      vuint32_t WDIL:1;
      vuint32_t BOL:1;
      vuint32_t EWL:1;
      vuint32_t EPL:1;
      vuint32_t ELOL:1;
      vuint32_t BEUL:1;
      vuint32_t BECL:1;
      vuint32_t DRXL:1;                /* Message stored to Dedicated Rx Buffer Interrupt Line */
      vuint32_t TOOL:1;
      vuint32_t MRAFL:1;
      vuint32_t TSWL:1;
      vuint32_t TEFLL:1;
      vuint32_t TEFFL:1;
      vuint32_t TEFWL:1;
      vuint32_t TEFNL:1;
      vuint32_t TFEL:1;
      vuint32_t TCFL:1;
      vuint32_t TCL:1;
      vuint32_t HPML:1;
      vuint32_t RF1LL:1;
      vuint32_t RF1FL:1;
      vuint32_t RF1WL:1;
      vuint32_t RF1NL:1;
      vuint32_t RF0LL:1;
      vuint32_t RF0FL:1;
      vuint32_t RF0WL:1;
      vuint32_t RF0NL:1;
    } B;
  } ILS;

  union {                              /* Interrupt Line Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t EINT1:1;
      vuint32_t EINT0:1;
    } B;
  } ILE;

  uint8_t M_CAN_reserved3[32];
  union {                              /* Global Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ANFS:2;
      vuint32_t ANFE:2;
      vuint32_t RRFS:1;
      vuint32_t RRFE:1;
    } B;
  } GFC;

  union {                              /* Standard ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t LSS:8;
      vuint32_t FLSSA:14;
      vuint32_t  :2;
    } B;
  } SIDFC;

  union {                              /* Extended ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :9;
      vuint32_t LSE:7;
      vuint32_t FLESA:14;
      vuint32_t  :2;
    } B;
  } XIDFC;

  uint8_t M_CAN_reserved4[4];
  union {                              /* Extended ID and Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t EIDM:29;
    } B;
  } XIDAM;

  union {                              /* High Priority Message Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FLST:1;
      vuint32_t FIDX:7;
      vuint32_t MSI:2;
      vuint32_t BIDX:6;
    } B;
  } HPMS;

  union {                              /* New Data 1 Register */
    vuint32_t R;
    struct {
      vuint32_t ND1:32;                /* New Data[0:31] */
    } B;
  } NDAT1;

  union {                              /* New Data 2 Register */
    vuint32_t R;
    struct {
      vuint32_t ND2:32;                /* New Data[32:63] */
    } B;
  } NDAT2;

  union {                              /* Rx FIFO 0 Configuration */
    vuint32_t R;
    struct {
      vuint32_t F0OM:1;                /* FIFO 0 Operation Mode */
      vuint32_t F0WM:7;
      vuint32_t  :2;
      vuint32_t F0S:6;
      vuint32_t F0SA:14;
      vuint32_t  :2;
    } B;
  } RXF0C;

  union {                              /* Rx FIFO 0 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t RF0L:1;
      vuint32_t F0F:1;
      vuint32_t  :2;
      vuint32_t F0PI:6;                /* Rx FIFO 0 Put Index */
      vuint32_t  :2;
      vuint32_t F0GI:6;
      vuint32_t  :1;
      vuint32_t F0FL:7;
    } B;
  } RXF0S;

  union {                              /* Rx FIFO 0 Acknowledge Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F0AI:6;
    } B;
  } RXF0A;

  union {                              /* Rx Buffer Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RBSA:14;               /* Rx Buffer Start Address */
      vuint32_t  :2;
    } B;
  } RXBC;

  union {                              /* Rx FIFO 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t F1OM:1;                /* FIFO 1 Operation Mode */
      vuint32_t F1WM:7;
      vuint32_t  :1;
      vuint32_t F1S:7;
      vuint32_t F1SA:14;
      vuint32_t  :2;
    } B;
  } RXF1C;

  union {                              /* Rx FIFO 1 Status Register */
    vuint32_t R;
    struct {
      vuint32_t DMS:2;
      vuint32_t  :4;
      vuint32_t RF1L:1;
      vuint32_t F1F:1;
      vuint32_t  :2;
      vuint32_t F1PI:6;                /* Rx FIFO 1 Put Index */
      vuint32_t  :2;
      vuint32_t F1G1:6;
      vuint32_t  :1;
      vuint32_t F1FL:7;
    } B;
  } RXF1S;

  union {                              /* Rx FIFO 1 Acknowledge Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F1AI:6;
    } B;
  } RXF1A;

  union {                              /* Rx Buffer / FIFO Element Size Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t RBDS:3;                /* Rx Buffer Data Field Size */
      vuint32_t  :1;
      vuint32_t F1DS:3;                /* Rx FIFO 1 Data Field Size */
      vuint32_t  :1;
      vuint32_t F0DS:3;                /* Rx FIFO 0 Data Field Size */
    } B;
  } RXESC;

  union {                              /* Tx Buffer Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TQFM:1;
      vuint32_t TQFS:6;
      vuint32_t  :2;
      vuint32_t NDTB:6;
      vuint32_t TBSA:14;
      vuint32_t  :2;
    } B;
  } TXBC;

  union {                              /* Tx FIFO/Queue Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t TFQF:1;
      vuint32_t TFQPI:5;
      vuint32_t  :3;
      vuint32_t TFGI:5;                /* Tx FIFO Get Index */
      vuint32_t  :2;
      vuint32_t TFFL:6;
    } B;
  } TXFQS;

  union {                              /* Tx Buffer Element Size Configuration */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t TBDS:3;
    } B;
  } TXESC;

  union {                              /* Tx Buffer Request Pending Register */
    vuint32_t R;
    struct {
      vuint32_t TRP:32;                /* Transmission Request Pending */
    } B;
  } TXBRP;

  union {                              /* Tx Buffer Add Request register */
    vuint32_t R;
    struct {
      vuint32_t AR:32;                 /* Add Request */
    } B;
  } TXBAR;

  union {                              /* Tx Buffer Cancellation Request register */
    vuint32_t R;
    struct {
      vuint32_t CR:32;                 /* Cancellation Request */
    } B;
  } TXBCR;

  union {                              /* Tx Buffer Transmission Occurred register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;                 /* Transmission Occurred */
    } B;
  } TXBTO;

  union {                              /* Tx Buffer Cancellation Finished register */
    vuint32_t R;
    struct {
      vuint32_t CF:32;                 /* Cancellation Finished */
    } B;
  } TXBCF;

  union {                              /* Tx Buffer Transmission Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t TIE:32;
    } B;
  } TXBTIE;

  union {                              /* Tx Buffer Cancellation Finished Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t CFIE:32;
    } B;
  } TXBCIE;

  uint8_t M_CAN_reserved5[8];
  union {                              /* Tx Event FIFO Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t EFWM:6;
      vuint32_t  :2;
      vuint32_t EFS:6;
      vuint32_t EFSA:14;
      vuint32_t  :2;
    } B;
  } TXEFC;

  union {                              /* Tx Event FIFO Status register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t TEFL:1;
      vuint32_t EFF:1;
      vuint32_t  :3;
      vuint32_t EFPI:5;
      vuint32_t  :3;
      vuint32_t EFGI:5;
      vuint32_t  :2;
      vuint32_t EFFL:6;
    } B;
  } TXEFS;

  union {                              /* Tx Event FIFO Acknowledge register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t EFAI:5;
    } B;
  } TXEFA;
};


/* ============================================================================
   =============================== Module: M_TTCAN ============================
   ============================================================================ */

struct M_TTCAN_tag {
  union {                              /* Core Release Register */
    vuint32_t R;
    struct {
      vuint32_t REL:4;
      vuint32_t STEP:4;
      vuint32_t SUBSTEP:4;
      vuint32_t YEAR:4;
      vuint32_t MON:8;
      vuint32_t DAY:8;
    } B;
  } CREL;

  union {                              /* Endian Register */
    vuint32_t R;
    struct {
      vuint32_t ETV:32;
    } B;
  } ENDN;

  uint8_t M_TTCAN_reserved0[4];
  union {                              /* Fast Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t TDCO:3;                /* Transceiver Delay Compensation Offset */
      vuint32_t TDC:1;                 /* Transceiver Delay Compensation */
      vuint32_t  :1;
      vuint32_t FBRP:12;               /* Fast Baud Rate Prescaler */
      vuint32_t  :3;
      vuint32_t FTSEG1:4;              /* Fast time segment before sample point */
      vuint32_t  :1;
      vuint32_t FTSEG2:3;              /* Fast time segment before sample point */
      vuint32_t  :2;
      vuint32_t FSJW:2;                /* Fast (Re) Synchronization Jump Width */
    } B;
  } FBTP;

  union {                              /* Test Register */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t TDCV:5;                /* Transceiver Delay Compensation Value */
      vuint32_t RX:1;
      vuint32_t TX:2;
      vuint32_t LBCK:1;
      vuint32_t CAT:1;                 /* Check ASC Transmit Control */
      vuint32_t CAM:1;                 /* Check ASC Multiplexer Control */
      vuint32_t TAT:1;                 /* Test ASC Transmit Control */
      vuint32_t TAM:1;                 /* Test ASC Multiplexer Control */
    } B;
  } TEST;

  union {                              /* RAM Watchdog Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t WDV:8;
      vuint32_t WDC:8;
    } B;
  } RWD;

  union {                              /* CC Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t FDBS:1;                /* Long Frame Mode Active */
      vuint32_t FDO:1;                 /* Fast Frame Mode Active */
      vuint32_t CMR:2;                 /* CAN Mode Request */
      vuint32_t CME:2;                 /* CAN Mode Enable */
      vuint32_t TEST:1;
      vuint32_t DAR:1;
      vuint32_t MON:1;
      vuint32_t CSR:1;
      vuint32_t CSA:1;
      vuint32_t ASM:1;                 /* ASM Restricted Operation Mode */
      vuint32_t CCE:1;
      vuint32_t INIT:1;
    } B;
  } CCCR;

  union {                              /* Bit Timing and Prescaler Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t BRP:10;                /* Baud Rate Prescaler */
      vuint32_t  :2;
      vuint32_t TSEG1:6;
      vuint32_t TSEG2:4;               /* Time segment after sample point */
      vuint32_t SJW:4;                 /* (Re) Synchronization Jump Width */
    } B;
  } BTP;

  union {                              /* Timestamp Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t TCP:4;
      vuint32_t  :14;
      vuint32_t TSS:2;
    } B;
  } TSCC;

  union {                              /* Timestamp Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TSC:16;
    } B;
  } TSCV;

  union {                              /* Timeout Counter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t TOP:16;
      vuint32_t  :13;
      vuint32_t TOS:2;
      vuint32_t ETOC:1;
    } B;
  } TOCC;

  union {                              /* Timeout Counter Value Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TOC:16;
    } B;
  } TOCV;

  uint8_t M_TTCAN_reserved1[16];
  union {                              /* Error Counter Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t CEL:8;
      vuint32_t RP:1;
      vuint32_t REC:7;
      vuint32_t TEC:8;
    } B;
  } ECR;

  union {                              /* Protocol Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t REDL:1;                /* Received a CAN FD Message */
      vuint32_t RBRS:1;                /* BRS flag of last received CAN FD Message */
      vuint32_t RESI:1;                /* ESI CAN FD Message with ESI flag */
      vuint32_t FLEC:3;                /* Fast Last Error Code */
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ACT:2;
      vuint32_t LEC:3;
    } B;
  } PSR;

  uint8_t M_TTCAN_reserved2[8];
  union {                              /* Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t STE:1;
      vuint32_t FOE:1;
      vuint32_t ACKE:1;
      vuint32_t BE:1;
      vuint32_t CRCE:1;
      vuint32_t WDI:1;
      vuint32_t BO:1;
      vuint32_t EW:1;
      vuint32_t EP:1;
      vuint32_t ELO:1;
      vuint32_t BEU:1;
      vuint32_t BEC:1;
      vuint32_t DRX:1;                 /* Message stored to Dedicated Rx Buffer */
      vuint32_t TOO:1;
      vuint32_t UMD:1;
      vuint32_t TSW:1;
      vuint32_t TEFL:1;
      vuint32_t TEFF:1;
      vuint32_t TEFW:1;
      vuint32_t TEFN:1;
      vuint32_t TFE:1;
      vuint32_t TCF:1;
      vuint32_t TC:1;
      vuint32_t HPM:1;
      vuint32_t RF1L:1;
      vuint32_t RF1F:1;
      vuint32_t RF1W:1;
      vuint32_t RF1N:1;
      vuint32_t RF0L:1;
      vuint32_t RF0F:1;
      vuint32_t RF0W:1;
      vuint32_t RF0N:1;
    } B;
  } IR;

  union {                              /* Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t STEE:1;
      vuint32_t FOEE:1;
      vuint32_t ACKEE:1;
      vuint32_t BEE:1;
      vuint32_t CRCEE:1;
      vuint32_t WDIE:1;
      vuint32_t BOE:1;
      vuint32_t EWE:1;
      vuint32_t EPE:1;
      vuint32_t ELOE:1;
      vuint32_t BEUE:1;
      vuint32_t BECE:1;
      vuint32_t DRXE:1;                /* Message stored to Dedicated Rx Buffer Interrupt Enable */
      vuint32_t TOOE:1;
      vuint32_t UMDE:1;
      vuint32_t TSWE:1;
      vuint32_t TEFLE:1;
      vuint32_t TEFFE:1;
      vuint32_t TEFWE:1;
      vuint32_t TEFNE:1;
      vuint32_t TFEE:1;
      vuint32_t TCFE:1;
      vuint32_t TCE:1;
      vuint32_t HPME:1;
      vuint32_t RF1LE:1;
      vuint32_t RF1FE:1;
      vuint32_t RF1WE:1;
      vuint32_t RF1NE:1;
      vuint32_t RF0LE:1;
      vuint32_t RF0FE:1;
      vuint32_t RF0WE:1;
      vuint32_t RF0NE:1;
    } B;
  } IE;

  union {                              /* Interrupt Line Select Register */
    vuint32_t R;
    struct {
      vuint32_t STEL:1;
      vuint32_t FOEL:1;
      vuint32_t ACKEL:1;
      vuint32_t BEL:1;
      vuint32_t CRCEL:1;
      vuint32_t WDIL:1;
      vuint32_t BOL:1;
      vuint32_t EWL:1;
      vuint32_t EPL:1;
      vuint32_t ELOL:1;
      vuint32_t BEUL:1;
      vuint32_t BECL:1;
      vuint32_t DRXL:1;                /* Message stored to Dedicated Rx Buffer Interrupt Line */
      vuint32_t TOOL:1;
      vuint32_t UMDL:1;
      vuint32_t TSWL:1;
      vuint32_t TEFLL:1;
      vuint32_t TEFFL:1;
      vuint32_t TEFWL:1;
      vuint32_t TEFNL:1;
      vuint32_t TFEL:1;
      vuint32_t TCFL:1;
      vuint32_t TCL:1;
      vuint32_t HPML:1;
      vuint32_t RF1LL:1;
      vuint32_t RF1FL:1;
      vuint32_t RF1WL:1;
      vuint32_t RF1NL:1;
      vuint32_t RF0LL:1;
      vuint32_t RF0FL:1;
      vuint32_t RF0WL:1;
      vuint32_t RF0NL:1;
    } B;
  } ILS;

  union {                              /* Interrupt Line Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t EINT1:1;
      vuint32_t EINT0:1;
    } B;
  } ILE;

  uint8_t M_TTCAN_reserved3[32];
  union {                              /* Global Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ANFS:2;
      vuint32_t ANFE:2;
      vuint32_t RRFS:1;
      vuint32_t RRFE:1;
    } B;
  } GFC;

  union {                              /* Standard ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t LSS:8;
      vuint32_t FLSSA:14;
      vuint32_t  :2;
    } B;
  } SIDFC;

  union {                              /* Extended ID Filter Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :9;
      vuint32_t LSE:7;
      vuint32_t FLESA:14;
      vuint32_t  :2;
    } B;
  } XIDFC;

  uint8_t M_TTCAN_reserved4[4];
  union {                              /* Extended ID and Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t EIDM:29;
    } B;
  } XIDAM;

  union {                              /* High Priority Message Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FLST:1;
      vuint32_t FIDX:7;
      vuint32_t MSI:2;
      vuint32_t BIDX:6;
    } B;
  } HPMS;

  union {                              /* New Data 1 Register */
    vuint32_t R;
    struct {
      vuint32_t ND1:32;                /* New Data[0:31] */
    } B;
  } NDAT1;

  union {                              /* New Data 2 Register */
    vuint32_t R;
    struct {
      vuint32_t ND2:32;                /* New Data[63:32] */
    } B;
  } NDAT2;

  union {                              /* Rx FIFO 0 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F0WM:7;
      vuint32_t  :1;
      vuint32_t F0S:7;
      vuint32_t FOSA:14;
      vuint32_t  :2;
    } B;
  } RXF0C;

  union {                              /* Rx FIFO 0 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t RF0L:1;
      vuint32_t F0F:1;
      vuint32_t  :2;
      vuint32_t F0PI:6;
      vuint32_t  :2;
      vuint32_t F0GI:6;
      vuint32_t  :1;
      vuint32_t F0FL:7;
    } B;
  } RXF0S;

  union {                              /* Rx FIFO 0 Acknowledge Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F0AI:6;
    } B;
  } RXF0A;

  union {                              /* Rx Buffer Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RBSA:14;               /* Rx Buffer Start Address */
      vuint32_t  :2;
    } B;
  } RXBC;

  union {                              /* Rx FIFO 1 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F1WM:7;
      vuint32_t  :1;
      vuint32_t F1S:7;
      vuint32_t F1SA:14;
      vuint32_t  :2;
    } B;
  } RXF1C;

  union {                              /* Rx FIFO 1 Status Register */
    vuint32_t R;
    struct {
      vuint32_t DMS:2;                 /* Debug Message Status */
      vuint32_t  :4;
      vuint32_t RF1L:1;
      vuint32_t F1F:1;
      vuint32_t  :2;
      vuint32_t F1PI:6;
      vuint32_t  :2;
      vuint32_t F1GI:6;
      vuint32_t  :1;
      vuint32_t F1FL:7;
    } B;
  } RXF1S;

  union {                              /* Rx FIFO 1 Acknowledge register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F1A1:6;
    } B;
  } RXF1A;

  uint8_t M_TTCAN_reserved5[4];
  union {                              /* Tx Buffer Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t TFQM:1;
      vuint32_t TFQS:6;
      vuint32_t  :2;
      vuint32_t NDTB:6;
      vuint32_t TBSA:14;
      vuint32_t  :2;
    } B;
  } TXBC;

  union {                              /* Tx FIFO/Queue Status register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t TFQF:1;
      vuint32_t TFQPI:5;
      vuint32_t  :3;
      vuint32_t TFGI:5;
      vuint32_t  :2;
      vuint32_t TFFL:6;
    } B;
  } TXFQS;

  uint8_t M_TTCAN_reserved6[4];
  union {                              /* Tx Buffer Request Pending register */
    vuint32_t R;
    struct {
      vuint32_t TRP:32;
    } B;
  } TXBRP;

  union {                              /* Tx Buffer Add Request register */
    vuint32_t R;
    struct {
      vuint32_t AR:32;
    } B;
  } TXBAR;

  union {                              /* Tx Buffer Cancellation Request register */
    vuint32_t R;
    struct {
      vuint32_t CR:32;
    } B;
  } TXBCR;

  union {                              /* Tx Buffer Transmission Occurred register */
    vuint32_t R;
    struct {
      vuint32_t TO:32;
    } B;
  } TXBTO;

  union {                              /* Tx Buffer Cancellation Finished register */
    vuint32_t R;
    struct {
      vuint32_t CF:32;
    } B;
  } TXBCF;

  union {                              /* Tx Buffer Transmission Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t TIE:32;
    } B;
  } TXBTIE;

  union {                              /* Tx Buffer Cancellation Finished Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t CFIE:32;
    } B;
  } TXBCIE;

  uint8_t M_TTCAN_reserved7[8];
  union {                              /* Tx Event FIFO Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t EFWM:6;
      vuint32_t  :2;
      vuint32_t EFS:6;
      vuint32_t EFSA:14;
      vuint32_t  :2;
    } B;
  } TXEFC;

  union {                              /* Tx Event FIFO Status register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t TEFL:1;
      vuint32_t EFF:1;
      vuint32_t  :3;
      vuint32_t EFPI:5;
      vuint32_t  :3;
      vuint32_t EFGI:5;
      vuint32_t  :2;
      vuint32_t EFFL:6;
    } B;
  } TXEFS;

  union {                              /* Tx Event FIFO Acknowledge register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t EFAI:5;
    } B;
  } TXEFA;

  uint8_t M_TTCAN_reserved8[4];
  union {                              /* TT Trigger Memory Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :9;
      vuint32_t TME:7;
      vuint32_t TMSA:14;
      vuint32_t  :2;
    } B;
  } TTTMC;

  union {                              /* TT Reference Message Configuration register */
    vuint32_t R;
    struct {
      vuint32_t RMPS:1;
      vuint32_t XTD:1;
      vuint32_t  :1;
      vuint32_t RID:29;
    } B;
  } TTRMC;

  union {                              /* TT Operation Configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t EVTP:1;
      vuint32_t ECC:1;
      vuint32_t EGTF:1;
      vuint32_t AWL:8;
      vuint32_t EECS:1;
      vuint32_t IRTO:7;
      vuint32_t LDSDL:3;
      vuint32_t TM:1;
      vuint32_t GEN:1;
      vuint32_t  :1;
      vuint32_t OM:2;
    } B;
  } TTOCF;

  union {                              /* TT Matrix Limits register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t ENTT:12;
      vuint32_t  :4;
      vuint32_t TXEW:4;
      vuint32_t CSS:2;                 /* Cycle Start Synchronization */
      vuint32_t CCM:6;
    } B;
  } TTMLM;

  union {                              /* TUR Configuration register */
    vuint32_t R;
    struct {
      vuint32_t ELT:1;
      vuint32_t  :1;
      vuint32_t DC:14;
      vuint32_t NCL:16;
    } B;
  } TURCF;

  union {                              /* TT Operation Control register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LCKC:1;
      vuint32_t  :1;
      vuint32_t ESCN:1;
      vuint32_t NIG:1;
      vuint32_t TMG:1;
      vuint32_t FGP:1;
      vuint32_t GCS:1;
      vuint32_t TTIE:1;                /* Trigger Time Mark Interrupt Pulse Enable */
      vuint32_t TMC:2;
      vuint32_t RTIE:1;
      vuint32_t SWS:2;
      vuint32_t SWP:1;
      vuint32_t ECS:1;
      vuint32_t SGT:1;
    } B;
  } TTOCN;

  union {                              /* TT Global Time Preset register */
    vuint32_t R;
    struct {
      vuint32_t CTP:16;
      vuint32_t TP:16;
    } B;
  } TTGTP;

  union {                              /* TT Time Mark register */
    vuint32_t R;
    struct {
      vuint32_t LCKM:1;
      vuint32_t  :8;
      vuint32_t TICC:7;
      vuint32_t TM:16;
    } B;
  } TTTMK;

  union {                              /* TT Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t CER:1;
      vuint32_t AW:1;
      vuint32_t WT:1;
      vuint32_t IWT:1;
      vuint32_t ELC:1;
      vuint32_t SE2:1;
      vuint32_t SE1:1;
      vuint32_t TXO:1;
      vuint32_t TXU:1;
      vuint32_t GTE:1;
      vuint32_t GTD:1;
      vuint32_t GTW:1;
      vuint32_t SWE:1;
      vuint32_t TTMI:1;
      vuint32_t RTMI:1;
      vuint32_t SOG:1;
      vuint32_t CSM:1;
      vuint32_t SMC:1;
      vuint32_t SBC:1;
    } B;
  } TTIR;

  union {                              /* TT Interrupt Enable register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t CERE:1;
      vuint32_t AWE:1;
      vuint32_t WTE:1;
      vuint32_t IWTE:1;
      vuint32_t ELCE:1;
      vuint32_t SE2E:1;
      vuint32_t SE1E:1;
      vuint32_t TXOE:1;
      vuint32_t TXUE:1;
      vuint32_t GTEE:1;
      vuint32_t GTDE:1;
      vuint32_t GTWE:1;
      vuint32_t SWEE:1;
      vuint32_t TTMIE:1;
      vuint32_t RTMIE:1;
      vuint32_t SOGE:1;
      vuint32_t CSME:1;
      vuint32_t SMCE:1;
      vuint32_t SBCE:1;
    } B;
  } TTIE;

  union {                              /* TT Interrupt Line Select register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t CERL:1;
      vuint32_t AWL:1;
      vuint32_t WTL:1;
      vuint32_t IWTL:1;
      vuint32_t ELCL:1;
      vuint32_t SE2L:1;
      vuint32_t SE1L:1;
      vuint32_t TXOL:1;
      vuint32_t TXUL:1;
      vuint32_t GTEL:1;
      vuint32_t GTDL:1;
      vuint32_t GTWE:1;
      vuint32_t SWEL:1;
      vuint32_t TTMIL:1;
      vuint32_t RTMIL:1;
      vuint32_t SOGL:1;
      vuint32_t CSML:1;
      vuint32_t SMCL:1;
      vuint32_t SBCL:1;
    } B;
  } TTILS;

  union {                              /* TT Operation Status register */
    vuint32_t R;
    struct {
      vuint32_t SPL:1;
      vuint32_t WECS:1;
      vuint32_t AWE:1;
      vuint32_t WFE:1;
      vuint32_t GSI:1;
      vuint32_t TMP:3;
      vuint32_t GFI:1;
      vuint32_t WGTD:1;
      vuint32_t  :6;
      vuint32_t RTO:8;
      vuint32_t QCS:1;
      vuint32_t QGTP:1;
      vuint32_t SYS:2;
      vuint32_t MS:2;
      vuint32_t EL:2;
    } B;
  } TTOST;

  union {                              /* TUR Numerator Actual register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t NAV:18;
    } B;
  } TURNA;

  union {                              /* TT Local and Global Time register */
    vuint32_t R;
    struct {
      vuint32_t GT:16;
      vuint32_t LT:16;
    } B;
  } TTLGT;

  union {                              /* TT Cycle Time and Count register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t CC:6;
      vuint32_t CT:16;
    } B;
  } TTCTC;

  union {                              /* TT Capture Time register */
    vuint32_t R;
    struct {
      vuint32_t SWV:16;
      vuint32_t  :10;
      vuint32_t CCV:6;
    } B;
  } TTCPT;

  union {                              /* TT Cycle Sync Mark register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CSM:16;
    } B;
  } TTCSM;
};


/* ============================================================================
   =============================== Module: PASS ===============================
   ============================================================================ */

struct PASS_tag {
  union {                              /* Life Cycle Status Register */
    vuint32_t R;
    struct {
      vuint32_t CNS:1;
      vuint32_t JUN:1;
      vuint32_t FBE:1;
      vuint32_t  :21;
      vuint32_t LIFE:8;
    } B;
  } LCSTAT;

  uint8_t PASS_reserved0[4];
  union {                              /* Challenge Selector Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t GRP:2;
    } B;
  } CHSEL;

  uint8_t PASS_reserved1[4];
  union {                              /* Challenge Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t CMST:4;
    } B;
  } CSTAT;

  uint8_t PASS_reserved2[12];
  union {                              /* Challenge Input Register */
    vuint32_t R;
    struct {
      vuint32_t PW32:32;
    } B;
  } CIN[8];

  uint8_t PASS_reserved3[192];
  struct {
    union {                            /* Password Group n - Lock 0 Status Register */
      vuint32_t R;
      struct {
        vuint32_t TSLOCK:1;
        vuint32_t ATSL:1;
        vuint32_t LOWLOCK:14;
        vuint32_t MIDLOCK:16;
      } B;
    } LOCK0;
    union {                            /* Password Group n - Lock 1 Status Register */
      vuint32_t R;
      struct {
        vuint32_t  :16;
        vuint32_t HIGHLOCK:16;
      } B;
    } LOCK1;
    union {                            /* Password Group n - Lock 2 Status Register */
      vuint32_t R;
      struct {
        vuint32_t L_256LCK:32;
      } B;
    } LOCK2;
    union {                            /* Password Group n - Lock 3 Status Register */
      vuint32_t R;
      struct {
        vuint32_t PGL:1;
        vuint32_t DBL:1;
        vuint32_t MO:1;
        vuint32_t  :1;
        vuint32_t MSTR:4;
        vuint32_t  :3;
        vuint32_t RL4:1;
        vuint32_t RL3:1;
        vuint32_t RL2:1;
        vuint32_t RL1:1;
        vuint32_t RL0:1;
        vuint32_t U_256LCK:16;
      } B;
    } LOCK3;
  } PG[4];
};


/* ============================================================================
   =============================== Module: PBRIDGE ============================
   ============================================================================ */

struct PBRIDGE_tag {
  union {                              /* Master Privilege Register A */
    vuint32_t R;
    struct {
      vuint32_t MPROT0:4;
      vuint32_t MPROT1:4;
      vuint32_t MPROT2:4;
      vuint32_t MPROT3:4;
      vuint32_t MPROT4:4;
      vuint32_t MPROT5:4;
      vuint32_t MPROT6:4;
      vuint32_t MPROT7:4;
    } B;
  } MPRA;

  union {                              /* Master Privilege Register B */
    vuint32_t R;
    struct {
      vuint32_t MPROT8:4;
      vuint32_t MPROT9:4;
      vuint32_t MPROT10:4;
      vuint32_t MPROT11:4;
      vuint32_t MPROT12:4;
      vuint32_t MPROT13:4;
      vuint32_t MPROT14:4;
      vuint32_t MPROT15:4;
    } B;
  } MPRB;

  uint8_t PBRIDGE_reserved0[248];
  union {                              /* Peripheral Access Control Register */
    vuint32_t R;
    struct {
      vuint32_t PACRa:4;
      vuint32_t PACRb:4;
      vuint32_t PACRc:4;
      vuint32_t PACRd:4;
      vuint32_t PACRe:4;
      vuint32_t PACRf:4;
      vuint32_t PACRg:4;
      vuint32_t PACRh:4;
    } B;
  } PACR[8];

  uint8_t PBRIDGE_reserved1[32];
  union {                              /* Off-platform Peripheral Access Control Register */
    vuint32_t R;
    struct {
      vuint32_t OPACRa:4;
      vuint32_t OPACRb:4;
      vuint32_t OPACRc:4;
      vuint32_t OPACRd:4;
      vuint32_t OPACRe:4;
      vuint32_t OPACRf:4;
      vuint32_t OPACRg:4;
      vuint32_t OPACRh:4;
    } B;
  } OPACR[32];
};


/* ============================================================================
   =============================== Module: PCM ================================
   ============================================================================ */

struct PCM_tag {
  union {                              /* FEC Burst Optimization Master Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t ACCERR:1;
      vuint32_t WBEN:1;
      vuint32_t RBEN:1;
      vuint32_t FXSBE:8;
    } B;
  } FBOMCR;

  union {                              /* IAHB Burst Enable 1 Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t RSV:3;
      vuint32_t  :5;
      vuint32_t PRE_DMA:1;
      vuint32_t BRE_DMA:1;
      vuint32_t BWE_DMA:1;
      vuint32_t  :5;
      vuint32_t PRE_S0:1;
      vuint32_t BRE_S0:1;
      vuint32_t BWE_S0:1;
      vuint32_t  :5;
      vuint32_t PRE_M3:1;
      vuint32_t BRE_M3:1;
      vuint32_t BWE_M3:1;
    } B;
  } IAHB_BE1;

  union {                              /* IAHB Burst Enable 2 Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t RSV:3;
      vuint32_t  :5;
      vuint32_t PRE_SIPI:1;
      vuint32_t BRE_SIPI:1;
      vuint32_t BWE_SIPI:1;
      vuint32_t  :5;
      vuint32_t PRE_FlexRay:1;
      vuint32_t BRE_FlexRay:1;
      vuint32_t BWE_FlexRay:1;
      vuint32_t  :5;
      vuint32_t PRE_FEC:1;
      vuint32_t BRE_FEC:1;
      vuint32_t BWE_FEC:1;
    } B;
  } IAHB_BE2;
};


/* ============================================================================
   =============================== Module: PFLASH =============================
   ============================================================================ */

struct PFLASH_tag {
  union {                              /* Platform Flash Configuration Register 1 */
    vuint32_t R;
    struct {
      vuint32_t P0_M15PFE:1;
      vuint32_t P0_M14PFE:1;
      vuint32_t P0_M13PFE:1;
      vuint32_t P0_M12PFE:1;
      vuint32_t P0_M11PFE:1;
      vuint32_t P0_M10PFE:1;
      vuint32_t P0_M9PFE:1;
      vuint32_t P0_M8PFE:1;
      vuint32_t P0_M7PFE:1;
      vuint32_t P0_M6PFE:1;
      vuint32_t P0_M5PFE:1;
      vuint32_t P0_M4PFE:1;
      vuint32_t P0_M3PFE:1;
      vuint32_t P0_M2PFE:1;
      vuint32_t P0_M1PFE:1;
      vuint32_t P0_M0PFE:1;
      vuint32_t APC:3;
      vuint32_t RWSC:5;
      vuint32_t  :1;
      vuint32_t P0_DPFEN:1;
      vuint32_t  :1;
      vuint32_t P0_IPFEN:1;
      vuint32_t  :1;
      vuint32_t P0_PFLIM:2;
      vuint32_t P0_BFEN:1;
    } B;
  } PFCR1;

  union {                              /* Platform Flash Configuration Register 2 */
    vuint32_t R;
    struct {
      vuint32_t P1_M15PFE:1;
      vuint32_t P1_M14PFE:1;
      vuint32_t P1_M13PFE:1;
      vuint32_t P1_M12PFE:1;
      vuint32_t P1_M11PFE:1;
      vuint32_t P1_M10PFE:1;
      vuint32_t P1_M9PFE:1;
      vuint32_t P1_M8PFE:1;
      vuint32_t P1_M7PFE:1;
      vuint32_t P1_M6PFE:1;
      vuint32_t P1_M5PFE:1;
      vuint32_t P1_M4PFE:1;
      vuint32_t P1_M3PFE:1;
      vuint32_t P1_M2PFE:1;
      vuint32_t P1_M1PFE:1;
      vuint32_t P1_M0PFE:1;
      vuint32_t  :9;
      vuint32_t P1_DPFEN:1;
      vuint32_t  :1;
      vuint32_t P1_IPFEN:1;
      vuint32_t  :1;
      vuint32_t P1_PFLIM:2;
      vuint32_t P1_BFEN:1;
    } B;
  } PFCR2;

  union {                              /* Platform Flash Configuration Register 3 */
    vuint32_t R;
    struct {
      vuint32_t P0_WCFG:2;
      vuint32_t P1_WCFG:2;
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t BDRM:1;
      vuint32_t  :3;
      vuint32_t BAF_DIS:1;
      vuint32_t ARBM:2;
      vuint32_t  :2;
      vuint32_t  :11;
      vuint32_t  :1;
    } B;
  } PFCR3;

  union {                              /* Platform Flash Access Protection Register */
    vuint32_t R;
    struct {
      vuint32_t M0AP:2;
      vuint32_t M1AP:2;
      vuint32_t M2AP:2;
      vuint32_t M3AP:2;
      vuint32_t M4AP:2;
      vuint32_t M5AP:2;
      vuint32_t M6AP:2;
      vuint32_t M7AP:2;
      vuint32_t M8AP:2;
      vuint32_t M9AP:2;
      vuint32_t M10AP:2;
      vuint32_t M11AP:2;
      vuint32_t M12AP:2;
      vuint32_t M13AP:2;
      vuint32_t M14AP:2;
      vuint32_t M15AP:2;
    } B;
  } PFAPR;

  union {                              /* Platform Flash Remap Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t SAFE_CAL:1;
      vuint32_t  :3;
      vuint32_t IRMEN:1;
      vuint32_t  :3;
      vuint32_t GRMEN:1;
    } B;
  } PFCRCR;

  union {                              /* Platform Flash Remap Descriptor Enable Register */
    vuint32_t R;
    struct {
      vuint32_t CRD0EN:1;
      vuint32_t CRD1EN:1;
      vuint32_t CRD2EN:1;
      vuint32_t CRD3EN:1;
      vuint32_t CRD4EN:1;
      vuint32_t CRD5EN:1;
      vuint32_t CRD6EN:1;
      vuint32_t CRD7EN:1;
      vuint32_t CRD8EN:1;
      vuint32_t CRD9EN:1;
      vuint32_t CRD10EN:1;
      vuint32_t CRD11EN:1;
      vuint32_t CRD12EN:1;
      vuint32_t CRD13EN:1;
      vuint32_t CRD14EN:1;
      vuint32_t CRD15EN:1;
      vuint32_t CRD16EN:1;
      vuint32_t CRD17EN:1;
      vuint32_t CRD18EN:1;
      vuint32_t CRD19EN:1;
      vuint32_t CRD20EN:1;
      vuint32_t CRD21EN:1;
      vuint32_t CRD22EN:1;
      vuint32_t CRD23EN:1;
      vuint32_t CRD24EN:1;
      vuint32_t CRD25EN:1;
      vuint32_t CRD26EN:1;
      vuint32_t CRD27EN:1;
      vuint32_t CRD28EN:1;
      vuint32_t CRD29EN:1;
      vuint32_t CRD30EN:1;
      vuint32_t CRD31EN:1;
    } B;
  } PFCRDE;

  uint8_t PFLASH_reserved0[232];
  struct {
    union {                            /* Platform Flash Calibration Region Descriptor n Word0 */
      vuint32_t R;
      struct {
        vuint32_t LSTARTADDR:32;
      } B;
    } Word0;
    union {                            /* Platform Flash Calibration Region Descriptor n Word1 */
      vuint32_t R;
      struct {
        vuint32_t PSTARTADDR:32;
      } B;
    } Word1;
    union {                            /* Platform Flash Calibration Region Descriptor n Word2 */
      vuint32_t R;
      struct {
        vuint32_t M0EN:1;
        vuint32_t M1EN:1;
        vuint32_t M2EN:1;
        vuint32_t M3EN:1;
        vuint32_t M4EN:1;
        vuint32_t M5EN:1;
        vuint32_t M6EN:1;
        vuint32_t M7EN:1;
        vuint32_t M8EN:1;
        vuint32_t M9EN:1;
        vuint32_t M10EN:1;
        vuint32_t M11EN:1;
        vuint32_t M12EN:1;
        vuint32_t M13EN:1;
        vuint32_t M14EN:1;
        vuint32_t M15EN:1;
        vuint32_t  :11;
        vuint32_t CRDSize:5;
      } B;
    } Word2;
    uint8_t PFCRD_reserved0[4];
  } PFCRD[32];
};


/* ============================================================================
   =============================== Module: PIT ================================
   ============================================================================ */

struct PIT_tag {
  union {                              /* PIT Module Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t MDIS_RTI:1;
      vuint32_t MDIS:1;
      vuint32_t FRZ:1;
    } B;
  } MCR;

  uint8_t PIT_reserved0[220];
  union {                              /* PIT Upper Lifetime Timer Register */
    vuint32_t R;
    struct {
      vuint32_t LTH:32;
    } B;
  } LTMR64H;

  union {                              /* PIT Lower Lifetime Timer Register */
    vuint32_t R;
    struct {
      vuint32_t LTL:32;
    } B;
  } LTMR64L;

  uint8_t PIT_reserved1[8];
  union {                              /* PIT RTI Timer Load Value Register */
    vuint32_t R;
    struct {
      vuint32_t TSV:32;
    } B;
  } RTI_LDVAL;

  union {                              /* PIT RTI Current Timer Value Register */
    vuint32_t R;
    struct {
      vuint32_t TVL:32;
    } B;
  } RTI_CVAL;

  union {                              /* PIT RTI Timer Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :29;
      vuint32_t CHN:1;
      vuint32_t TIE:1;
      vuint32_t TEN:1;
    } B;
  } RTI_TCTRL;

  union {                              /* PIT RTI Timer Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t TIF:1;
    } B;
  } RTI_TFLG;

  struct {
    union {                            /* PIT Timer Load Value Register n */
      vuint32_t R;
      struct {
        vuint32_t TSV:32;
      } B;
    } LDVAL;
    union {                            /* PIT Current Timer Value Register n */
      vuint32_t R;
      struct {
        vuint32_t TVL:32;
      } B;
    } CVAL;
    union {                            /* PIT Timer Control Register n */
      vuint32_t R;
      struct {
        vuint32_t  :29;
        vuint32_t CHN:1;
        vuint32_t TIE:1;
        vuint32_t TEN:1;
      } B;
    } TCTRL;
    union {                            /* PIT Timer Flag Register n */
      vuint32_t R;
      struct {
        vuint32_t  :31;
        vuint32_t TIF:1;
      } B;
    } TFLG;
  } CH[8];
};


/* ============================================================================
   =============================== Module: PLLDIG =============================
   ============================================================================ */

struct PLLDIG_tag {
  union {                              /* PLLDIG PLL0 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t CLKCFG:2;              /* Clock Configuration */
      vuint32_t EXPDIE:1;              /* External Power Down Cycle Complete indication interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLIE:1;               /* Loss-of-lock interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL0CR;

  union {                              /* PLLDIG PLL0 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t EXTPDF:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLF:1;
      vuint32_t LOCK:1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL0SR;

  union {                              /* PLLDIG PLL0 Divider Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t RFDPHI1:4;             /* PHI1 reduced frequency divider. */
      vuint32_t  :5;
      vuint32_t RFDPHI:6;              /* PHI reduced frequency divider. */
      vuint32_t  :1;
      vuint32_t PREDIV:3;              /* Input clock predivider. */
      vuint32_t  :5;
      vuint32_t MFD:7;                 /* Loop multiplication factor divider. */
    } B;
  } PLL0DV;

  uint8_t PLLDIG_reserved0[20];
  union {                              /* PLLDIG PLL1 Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t  :1;
      vuint32_t CLKCFG:2;              /* Clock Configuration */
      vuint32_t EXPDIE:1;              /* External Power Down Cycle Complete indication interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLIE:1;               /* Loss-of-lock interrupt enable. */
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL1CR;

  union {                              /* PLLDIG PLL1 Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t EXTPDF:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t LOLF:1;
      vuint32_t LOCK:1;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } PLL1SR;

  union {                              /* PLLDIG PLL1 Divider Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t RFDPHI:6;
      vuint32_t  :5;
      vuint32_t  :4;
      vuint32_t MFD:7;                 /* Loop multiplication factor divider. */
    } B;
  } PLL1DV;

  union {                              /* PLLDIG PLL1 Frequency Modulation Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t MODEN:1;               /* Modulation enable. */
      vuint32_t MODSEL:1;              /* Modulation selection. */
      vuint32_t MODPRD:13;             /* Modulation period. */
      vuint32_t  :1;
      vuint32_t INCSTP:15;             /* Increment step. */
    } B;
  } PLL1FM;

  union {                              /* PLLDIG PLL1 Fractional Divide Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t FDEN:1;                /* Fractional Divide Enable */
      vuint32_t  :12;
      vuint32_t DTHDIS:2;              /* Dither Disable. */
      vuint32_t  :4;
      vuint32_t FRCDIV:12;
    } B;
  } PLL1FD;
};


/* ============================================================================
   =============================== Module: PMCDIG =============================
   ============================================================================ */

struct PMCDIG_tag {
  union {                              /* Supply Gauge Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t TS3:1;                 /* TS3 over temperature detect flag. */
      vuint32_t TS2:1;                 /* TS2 over temperature detect flag. */
      vuint32_t TS0:1;                 /* TS0 under temperature detect flag. */
      vuint32_t  :8;
      vuint32_t VD15:1;                /* VD15 high-voltage detect flag. */
      vuint32_t VD14:1;                /* VD14 low-voltage detect flag. */
      vuint32_t VD13:1;                /* VD13 low-voltage detect flag. */
      vuint32_t VD12:1;                /* VD12 high-voltage detect flag. */
      vuint32_t  :1;
      vuint32_t VD10:1;                /* HVD occurrence detected on the high voltage 3.60 V supply. */
      vuint32_t VD9:1;                 /* VD9 low-voltage detect flag. */
      vuint32_t VD8:1;                 /* VD8 high-voltage detect flag. */
      vuint32_t VD7:1;                 /* VD7 high-voltage detect flag. */
      vuint32_t  :2;
      vuint32_t VD4:1;                 /* VD4 low-voltage detect flag. */
      vuint32_t VD3:1;                 /* VD3 low-voltage detect flag. */
      vuint32_t  :3;                   /* Reserved */
    } B;
  } GR_S;

  union {                              /* Pending Gauge Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t VD15_A:1;              /* VD15_A high-voltage detect flag. */
      vuint32_t VD15_C:1;              /* VD15_C high-voltage detect flag. */
      vuint32_t  :1;
      vuint32_t VD14_A:1;              /* VD14_A low-voltage detect flag. */
      vuint32_t VD14_IM:1;             /* VD14_IM low-voltage detect flag. */
      vuint32_t  :2;
      vuint32_t VD13_IM:1;             /* VD13_IM low-voltage detect flag. */
      vuint32_t VD12_F:1;              /* VD12_F high-voltage detect flag. */
      vuint32_t VD10_A:1;              /* VD10_A low-voltage detect flag. */
      vuint32_t VD10_F:1;              /* VD10_F low-voltage detect flag. */
      vuint32_t VD9_O:1;               /* VD9_O low-voltage detect flag. */
      vuint32_t VD9_IF2:1;             /* VD9_IF2 low-voltage detect flag. */
      vuint32_t VD9_IF:1;              /* VD9_IF low-voltage detect flag. */
      vuint32_t VD9_IJ:1;              /* VD9_IJ low-voltage detect flag. */
      vuint32_t VD9_IM:1;              /* VD9_IM low-voltage detect flag. */
      vuint32_t VD9_F:1;               /* VD9_F low-voltage detect flag. */
      vuint32_t VD9_EBI:1;             /* VD9_EBI low-voltage detect flag. */
      vuint32_t VD9_C:1;               /* VD9_C low-voltage detect flag. */
      vuint32_t VD8_C:1;               /* VD8_C high-voltage detect flag. */
      vuint32_t VD8_F:1;               /* VD8_F high-voltage detect flag. */
      vuint32_t VD7_C:1;               /* VD7_C high-voltage detect flag. */
      vuint32_t VD4_C:1;               /* VD4_C low-voltage detect flag. */
      vuint32_t VD3_P:1;               /* VD3_P low-voltage detect flag. */
      vuint32_t VD3_F:1;               /* VD3_F low-voltage detect flag. */
      vuint32_t VD3_C:1;               /* VD3_C low-voltage detect flag. */
    } B;
  } GR_P;

  union {                              /* Interrupt Enable Pending Register */
    vuint32_t R;
    struct {
      vuint32_t IE_EN:1;
      vuint32_t  :5;
      vuint32_t VD15IE_A:1;            /* VD15IE_A Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD15IE_C:1;            /* VD15IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t  :1;
      vuint32_t VD14IE_A:1;            /* VD14IE_A Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD14IE_IM:1;           /* VD14IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t  :2;
      vuint32_t VD13IE_IM:1;           /* VD13IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD12IE_F:1;            /* VD12IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD10IE_A:1;            /* VD10IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD10IE_F:1;            /* VD10IE_A Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_O:1;             /* VD9IE_O Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IF2:1;           /* VD9IE_IF2 Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IF:1;            /* VD9IE_IF Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IJ:1;            /* VD9IE_IJ Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_IM:1;            /* VD9IE_IM Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_F:1;             /* VD9IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_EBI:1;           /* VD9IE_EBI Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD9IE_C:1;             /* VD9IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD8IE_C:1;             /* VD8IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD8IE_F:1;             /* VD8IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD7IE_C:1;             /* VD7IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD4IE_C:1;             /* VD4IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD3IE_P:1;             /* VD3IE_P Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD3IE_F:1;             /* VD3IE_F Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
      vuint32_t VD3IE_C:1;             /* VD3IE_C Interrupt Enable. This bit determines whether an interrupt is seen by the system when the voltage detect event occurs. */
    } B;
  } IE_P;

  uint8_t PMCDIG_reserved0[36];
  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t LVD3_P:1;              /* LVD3_P flag. */
      vuint32_t LVD3_F:1;              /* LVD3_F flag. */
      vuint32_t  :5;
      vuint32_t LVD3_C:1;              /* LVD3_C flag. */
    } B;
  } EPR_VD3;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t LVD3_P:1;              /* LVD3_P reset enable. */
      vuint32_t LVD3_F:1;              /* LVD3_F reset enable. */
      vuint32_t  :5;
      vuint32_t LVD3_C:1;              /* LVD3_C reset enable. */
    } B;
  } REE_VD3;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t LVD3_P:1;              /* LVD3_P reset event select. */
      vuint32_t LVD3_F:1;              /* LVD3_F reset event select. */
      vuint32_t  :5;
      vuint32_t LVD3_C:1;              /* LVD3_C reset event select. */
    } B;
  } RES_VD3;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t FEE3_P:1;              /* FEE3_P FCCU event enable. */
      vuint32_t FEE3_F:1;              /* FEE3_F FCCU event enable. */
      vuint32_t  :5;
      vuint32_t FEE3_C:1;              /* FEE3_C FCCU event enable. */
    } B;
  } FEE_VD3;

  union {                              /* LVD108 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t LVD4_C:1;              /* LVD4_C flag. */
    } B;
  } EPR_VD4;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t LVD4_C:1;              /* LVD4_C reset enable. */
    } B;
  } REE_VD4;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t LVD4_C:1;              /* LVD4_H reset event select. */
    } B;
  } RES_VD4;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t FEE4_C:1;              /* FEE4_C FCCU event enable. */
    } B;
  } FEE_VD4;

  uint8_t PMCDIG_reserved1[32];
  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t HVD7_C:1;              /* HVD7_C flag. */
    } B;
  } EPR_VD7;

  union {                              /* Reset Event Enable VD7 Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t HVD7_C:1;              /* HVD7_C reset enable. */
    } B;
  } REE_VD7;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t HVD7_C:1;              /* HVD7_C reset event select. */
    } B;
  } RES_VD7;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t  :9;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t FEE7_C:1;              /* FEE7_C FCCU event enable. This bit defines whether an HVD assertion on the supply of the cold point generates an FCCU event. */
    } B;
  } FEE_VD7;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD8_F:1;              /* HVD8_F flag. */
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t HVD8_C:1;              /* HVD8_C flag. */
    } B;
  } EPR_VD8;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD8_F:1;              /* HVD8_F reset enable. */
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t HVD8_C:1;              /* HVD8_C reset enable. */
    } B;
  } REE_VD8;

  union {                              /* Reset Event Select Registerr */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD8_F:1;              /* HVD8_F */
      vuint32_t  :5;                   /* Reserved. */
      vuint32_t HVD8_C:1;              /* HVD8_C reset event select. */
    } B;
  } RES_VD8;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FEE8_F:1;              /* FEE8_F FCCU event enable. */
      vuint32_t  :5;
      vuint32_t FEE8_C:1;              /* FEE8_C FCCU event enable. */
    } B;
  } FEE_VD8;

  union {                              /* LVD270 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t LVD9_O:1;              /* LVD9_O flag. */
      vuint32_t  :2;
      vuint32_t LVD9_IF2:1;            /* LVD9_IF2 flag. */
      vuint32_t LVD9_IF:1;             /* LVD9_IF flag. */
      vuint32_t LVD9_IJ:1;             /* LVD9_IJ flag. */
      vuint32_t LVD9_IM:1;             /* LVD9_IM flag. */
      vuint32_t  :1;
      vuint32_t LVD9_F:1;              /* LVD9_F flag. */
      vuint32_t  :2;
      vuint32_t LVD9_EBI:1;            /* LVD9_EBI flag. */
      vuint32_t  :2;
      vuint32_t LVD9_C:1;              /* LVD9_C flag. */
    } B;
  } EPR_VD9;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t LVD9_O:1;              /* LVD9_O reset enable. */
      vuint32_t  :2;
      vuint32_t LVD9_IF2:1;            /* LVD9_IF2 reset enable. */
      vuint32_t LVD9_IF:1;             /* LVD9_IF reset enable. */
      vuint32_t LVD9_IJ:1;             /* LVD9_IJ reset enable. */
      vuint32_t LVD9_IM:1;             /* LVD9_IM reset enable. */
      vuint32_t  :1;
      vuint32_t LVD9_F:1;              /* LVD9_F reset enable. */
      vuint32_t  :2;
      vuint32_t LVD9_EBI:1;            /* LVD9_EBI reset enable. */
      vuint32_t  :2;
      vuint32_t LVD9_C:1;              /* LVD9_C reset enable. */
    } B;
  } REE_VD9;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t LVD9_IF2:1;            /* LVD9_IF2 reset event select. */
      vuint32_t LVD9_IF:1;             /* LVD9_IF reset event select. */
      vuint32_t  :6;
      vuint32_t LVD9_EBI:1;            /* LVD9_EBI reset event select. */
      vuint32_t  :3;
    } B;
  } RES_VD9;

  union {                              /* FCCU Event Enable VD9 */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t FEE9_O:1;              /* FEE9_O FCCU event enable. */
      vuint32_t  :2;
      vuint32_t FEE9_IF2:1;            /* FEE9_IF2 FCCU event enable. */
      vuint32_t FEE9_IF:1;             /* FEE9_IF FCCU event enable. */
      vuint32_t FEE9_IJ:1;             /* FEE9_IJ FCCU event enable. */
      vuint32_t FEE9_IM:1;             /* FEE9_IM FCCU event enable. */
      vuint32_t  :1;
      vuint32_t FEE9_F:1;              /* FEE9_F FCCU event enable. */
      vuint32_t  :2;
      vuint32_t FEE9_EBI:1;            /* FEE9_EBI FCCU event enable. */
      vuint32_t  :2;
      vuint32_t FEE9_C:1;              /* FEE9_C FCCU event enable. */
    } B;
  } FEE_VD9;

  union {                              /* LVD295 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD10_A:1;             /* LVD10_A flag. */
      vuint32_t  :8;
      vuint32_t LVD10_F:1;             /* LVD10_F flag. */
      vuint32_t  :6;
    } B;
  } EPR_VD10;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD10_A:1;             /* LVD10_A reset enable. */
      vuint32_t  :8;
      vuint32_t LVD10_F:1;             /* LVD10_F reset enable. */
      vuint32_t  :6;
    } B;
  } REE_VD10;

  uint8_t PMCDIG_reserved2[4];
  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FEE10_A:1;             /* FEE10_A FCCU event enable. */
      vuint32_t  :8;
      vuint32_t FEE10_F:1;             /* FEE10_F FCCU event enable. */
      vuint32_t  :6;
    } B;
  } FEE_VD10;

  uint8_t PMCDIG_reserved3[16];
  union {                              /* HVD360 Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD12_F:1;             /* HVD12_F flag. */
      vuint32_t  :6;
    } B;
  } EPR_VD12;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD12_F:1;             /* HVD12_F reset enable. */
      vuint32_t  :6;
    } B;
  } REE_VD12;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t HVD12_F:1;             /* HVD12_F reset event select. */
      vuint32_t  :6;
    } B;
  } RES_VD12;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :25;
      vuint32_t FEE12_F:1;             /* FEE12_F FCCU event enable. */
      vuint32_t  :6;
    } B;
  } FEE_VD12;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t LVD13_IM:1;            /* LVD13_IM flag. */
      vuint32_t  :8;
    } B;
  } EPR_VD13;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t LVD13_IM:1;            /* LVD13_IM reset enable. */
      vuint32_t  :8;
    } B;
  } REE_VD13;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t LVD13_IM:1;            /* LVD13_IM reset event select. */
      vuint32_t  :8;
    } B;
  } RES_VD13;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :23;
      vuint32_t FEE13_IM:1;            /* FEE13_IM FCCU event enable. */
      vuint32_t  :8;
    } B;
  } FEE_VD13;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD14_A:1;             /* LVD14_A flag. */
      vuint32_t  :6;
      vuint32_t LVD14_IM:1;            /* LVD14_IM flag. */
      vuint32_t  :8;
    } B;
  } EPR_VD14;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD14_A:1;             /* LVD14_A reset enable. */
      vuint32_t  :6;
      vuint32_t LVD14_IM:1;            /* LVD14_IM reset enable. */
      vuint32_t  :8;
    } B;
  } REE_VD14;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LVD14_A:1;             /* LVD14_A reset event select. */
      vuint32_t  :6;
      vuint32_t LVD14_IM:1;            /* LVD14_IM reset event select. */
      vuint32_t  :8;
    } B;
  } RES_VD14;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FEE14_A:1;             /* FEE14_A FCCU event enable. */
      vuint32_t  :6;
      vuint32_t FEE14_IM:1;            /* FEE14_IM FCCU event enable. */
      vuint32_t  :8;
    } B;
  } FEE_VD14;

  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HVD15_A:1;             /* HVD15_A flag. */
      vuint32_t  :14;
      vuint32_t HVD15_C:1;             /* HVD15_C flag. */
    } B;
  } EPR_VD15;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HVD15_A:1;             /* HVD15_A reset enable. */
      vuint32_t  :14;
      vuint32_t HVD15_C:1;
    } B;
  } REE_VD15;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t HVD15_A:1;             /* HVD15_A reset event select. */
      vuint32_t  :14;
      vuint32_t HVD15_C:1;             /* HVD15_C reset event select. */
    } B;
  } RES_VD15;

  union {                              /* FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t FEE15_A:1;             /* FEE15_A FCCU event enable. */
      vuint32_t  :14;
      vuint32_t FEE15_C:1;             /* FEE15_C FCCU event enable. */
    } B;
  } FEE_VD15;

  uint8_t PMCDIG_reserved4[4];
  union {                              /* Voltage Supply for I/O Segment Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t VSIO_IF2:1;            /* VSIO_IF2 control. */
      vuint32_t VSIO_IF:1;             /* VSIO_IF control. */
      vuint32_t VSIO_IJ:1;             /* VSIO_IJ control. */
      vuint32_t VSIO_IM:1;             /* VSIO_IM control. */
      vuint32_t  :8;
    } B;
  } VSIO;

  uint8_t PMCDIG_reserved5[504];
  union {                              /* Event Pending Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TEMP_3:1;              /* TEMP_3 flag. */
      vuint32_t TEMP_2:1;              /* TEMP_2 flag. */
      vuint32_t  :1;
      vuint32_t TEMP_0:1;              /* TEMP_0 flag. */
    } B;
  } EPR_TD;

  union {                              /* Reset Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TEMP_3:1;              /* TEMP_3 reset enable. */
      vuint32_t TEMP_2:1;              /* TEMP_2 reset enable. */
      vuint32_t  :1;
      vuint32_t TEMP_0:1;              /* TEMP_0 reset enable. */
    } B;
  } REE_TD;

  union {                              /* Reset Event Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t TEMP_3:1;              /* TEMP_3 reset event select. */
      vuint32_t TEMP_2:1;              /* TEMP_2 reset event select. */
      vuint32_t  :1;
      vuint32_t TEMP_0:1;              /* TEMP_0 reset event select. */
    } B;
  } RES_TD;

  union {                              /* Temperature Sensor Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t TS3IE:1;               /* TS3IE Temperature Sensor input 3 Interrupt Enable. */
      vuint32_t TS2IE:1;               /* TS2IE Temperature Sensor input 0 Interrupt Enable. */
      vuint32_t TS0IE:1;               /* TS0IE Temperature Sensor input 0 Interrupt Enable. */
      vuint32_t  :1;
      vuint32_t TRIM_ADJ_OVER:4;       /* Customer adjustable over trim register. */
      vuint32_t  :2;
      vuint32_t TRIM_ADJ_UNDER:4;      /* Customer adjustable trim register. */
      vuint32_t DOUT_EN:1;             /* Digital Output Enable. */
      vuint32_t AOUT_EN:1;             /* Analog Output Enable. */
    } B;
  } CTL_TD;

  uint8_t PMCDIG_reserved6[8];
  union {                              /* Temp Sensor FCCU Event Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t FEE_TS3:1;             /* FEE_TS3 Temp Sensor FCCU event enable. */
      vuint32_t FEE_TS2:1;             /* FEE_TS2 Temp Sensor FCCU event enable. */
      vuint32_t  :1;
      vuint32_t FEE_TS0:1;             /* FEE_TS0 Temp Sensor FCCU event enable. */
    } B;
  } FEE_TD;

  uint8_t PMCDIG_reserved7[36];
  union {                              /* Voltage Detect User Mode Test Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;                   /* Reserved. */
      vuint32_t VOLT4_EN:1;            /* VOLT4 enable. */
      vuint32_t VOLT3_EN:1;            /* VOLT3 enable. */
      vuint32_t VOLT2_EN:1;            /* VOLT2 enable. */
      vuint32_t VOLT1_EN:1;            /* VOLT1 enable. */
      vuint32_t  :4;                   /* Reserved. */
      vuint32_t VOLT4:1;               /* VOLT4 flag. */
      vuint32_t VOLT3:1;               /* VOLT3 flag. */
      vuint32_t VOLT2:1;               /* VOLT2 flag. */
      vuint32_t VOLT1:1;               /* VOLT1 flag. */
      vuint32_t  :10;
      vuint32_t VD_UTST:6;             /* Voltage Detect: User Test. */
    } B;
  } VD_UTST;

  union {                              /* ADC Channel Select Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t ADC_CS:6;              /* ADC_CS Channel Select. */
    } B;
  } ADC_CH;

  uint8_t PMCDIG_reserved8[4];
  union {                              /* Voltage Regulator 1.2V Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t VREG1P2_DIS:1;         /* This bit controls if the AUX Regulator (Vreg1p2) is disabled. */
    } B;
  } VREG1P2_CTRL;

  union {                              /* Module Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;                  /* Reserved. */
      vuint32_t ADC_CHSEL_EN:1;        /* This bit allows the ADC_CS bits int he ADC_CH register to be enabled. */
      vuint32_t USER_SELF_TEST_EN:1;   /* This bit allows the VD_UTST bits int he VD_UTST register to be enabled. */
      vuint32_t  :6;                   /* Reserved. */
      vuint32_t TEST_PIN:1;            /* This bit is indicates the current value of the Test Pin. */
      vuint32_t  :6;                   /* Reserved. */
      vuint32_t SBRAM_BRDET:1;         /* SBRAM_BRDET. */
    } B;
  } MCR;
};


/* ============================================================================
   =============================== Module: PRAMC ==============================
   ============================================================================ */

struct PRAMC_tag {
  union {                              /* Platform RAM Configuration Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t PRI:2;                 /* AHB port arbitration mode. */
      vuint32_t P1_BO_DIS:1;           /* Port p1 read burst optimization disable. */
      vuint32_t P0_BO_DIS:1;           /* Port p0 read burst optimization disable. */
      vuint32_t P1_RB_DIS:1;           /* Port p1 read buffer disable. */
      vuint32_t P0_RB_DIS:1;           /* Port p0 read buffer disable. */
      vuint32_t  :3;
      vuint32_t FT_DIS:1;              /* Flow through disabled. */
    } B;
  } PRCR1;
};


/* ============================================================================
   =============================== Module: PSI5 ===============================
   ============================================================================ */

struct PSI5_tag {
  union {                              /* Global Control Register */
    vuint16_t R;
    struct {
      vuint16_t  :14;
      vuint16_t CTC_GED:1;
      vuint16_t GLOBAL_DISABLE_REQ:1;
    } B;
  } GCR;

  uint8_t PSI5_reserved0[6];
  union {                              /* PSI5 Channel Control Register */
    vuint32_t R;
    struct {
      vuint32_t CTC_GED_SEL:1;
      vuint32_t CTC_ED:1;
      vuint32_t  :1;
      vuint32_t MEM_DEPTH:5;
      vuint32_t  :3;
      vuint32_t ERROR_SELECT4:1;
      vuint32_t ERROR_SELECT3:1;
      vuint32_t ERROR_SELECT2:1;
      vuint32_t ERROR_SELECT1:1;
      vuint32_t ERROR_SELECT0:1;
      vuint32_t  :1;
      vuint32_t GTM_RESET_ASYNC_EN:1;
      vuint32_t  :3;
      vuint32_t DEBUG_EN:1;
      vuint32_t DEBUG_FREEZE_CTRL:1;
      vuint32_t SP_TS_CLK_SEL:1;
      vuint32_t  :2;
      vuint32_t FAST_CLR_SMC:1;
      vuint32_t FAST_CLR_PSI5:1;
      vuint32_t BIT_RATE:1;
      vuint32_t MODE:1;
      vuint32_t PSI5_CH_CONFIG:1;
      vuint32_t PSI5_CH_EN:1;
    } B;
  } CH0_PCCR;

  union {                              /* DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DMA_PM_DS_WM:5;
      vuint32_t  :5;
      vuint32_t IE_DMA_TF_SF:1;
      vuint32_t IE_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IE_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IE_DMA_PM_DS_UF:1;
      vuint32_t  :5;
      vuint32_t DMA_EN_SF:1;
      vuint32_t DMA_PM_DS_CONFIG:2;
    } B;
  } CH0_DCR;

  union {                              /* DMA Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t IS_DMA_TF_SF:1;
      vuint32_t IS_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IS_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IS_DMA_PM_DS_UF:1;
      vuint32_t  :8;
    } B;
  } CH0_DSR;

  union {                              /* General Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t IE_CESM:6;
      vuint32_t IE_STS:1;
      vuint32_t IE_DTS:1;
      vuint32_t IE_DSROW:1;
      vuint32_t IE_BROW:1;
      vuint32_t IE_PROW:1;
      vuint32_t IE_DSRR:1;
      vuint32_t IE_BRR:1;
      vuint32_t IE_PRR:1;
      vuint32_t  :2;
      vuint32_t IE_OWSM:6;
      vuint32_t  :2;
      vuint32_t IE_NVSM:6;
    } B;
  } CH0_GICR;

  union {                              /* New Data Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ND:32;
    } B;
  } CH0_NDICR;

  union {                              /* Overwrite Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_OW:32;
    } B;
  } CH0_OWICR;

  union {                              /* Error Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ERROR:32;
    } B;
  } CH0_EICR;

  union {                              /* General Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t IS_DB_FR:1;
      vuint32_t  :1;
      vuint32_t IS_CESM:6;
      vuint32_t IS_STS:1;
      vuint32_t IS_DTS:1;
      vuint32_t IS_DSROW:1;
      vuint32_t IS_BROW:1;
      vuint32_t IS_PROW:1;
      vuint32_t DSR_RDY:1;
      vuint32_t DBR_RDY:1;
      vuint32_t DPR_RDY:1;
      vuint32_t  :2;
      vuint32_t IS_OWSM:6;
      vuint32_t  :2;
      vuint32_t IS_NVSM:6;
    } B;
  } CH0_GISR;

  union {                              /* DMA PSI5 Message Register */
    vuint32_t R;
    struct {
      vuint32_t PSI5_RXDATA:32;
    } B;
  } CH0_DPMR;

  union {                              /* DMA SMC Frame Register */
    vuint32_t R;
    struct {
      vuint32_t SMC_RXDATA:32;
    } B;
  } CH0_DSFR;

  union {                              /* DMA Diagnostic Status Register */
    vuint32_t R;
    struct {
      vuint32_t DDS:32;
    } B;
  } CH0_DDSR;

  union {                              /* PSI5 Message Receive Register Low */
    vuint32_t R;
    struct {
      vuint32_t DATA_REGION:28;
      vuint32_t CRC:3;
      vuint32_t C:1;
    } B;
  } CH0_PMRRL;

  union {                              /* PSI5 Message Receive Register High */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F:1;
      vuint32_t EM:1;
      vuint32_t E:1;
      vuint32_t T:1;
      vuint32_t SlotCounter:3;
      vuint32_t TimeStampValue:24;
    } B;
  } CH0_PMRRH;

  struct {
    union {                            /* PSI5 Message Register Low i */
      vuint32_t R;
      struct {
        vuint32_t DATA_REGION:28;
        vuint32_t CRCP:3;
        vuint32_t C:1;
      } B;
    } PMRL;
    union {                            /* PSI5 Message Register High i */
      vuint32_t R;
      struct {
        vuint32_t O:1;
        vuint32_t F:1;
        vuint32_t EM:1;
        vuint32_t E:1;
        vuint32_t T:1;
        vuint32_t Slot_Counter:3;
        vuint32_t TimeStampValue:24;
      } B;
    } PMRH;
  } CH0[32];

  union {                              /* SMC Frame Register n */
    vuint32_t R;
    struct {
      vuint32_t SLOT_NO:3;
      vuint32_t CER:1;
      vuint32_t OW:1;
      vuint32_t CRC:6;
      vuint32_t C:1;
      vuint32_t ID:4;
      vuint32_t IDDATA:4;
      vuint32_t DATA:12;
    } B;
  } CH0_SFR[6];

  union {                              /* New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t NDS:32;
    } B;
  } CH0_NDSR;

  union {                              /* Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t OWS:32;
    } B;
  } CH0_OWSR;

  union {                              /* Error Indication Status Register */
    vuint32_t R;
    struct {
      vuint32_t ERROR:32;
    } B;
  } CH0_EISR;

  union {                              /* Set New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t SNDS:32;
    } B;
  } CH0_SNDSR;

  union {                              /* Set Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t SOWS:32;
    } B;
  } CH0_SOWSR;

  union {                              /* Set Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t SERROR:32;
    } B;
  } CH0_SEISR;

  union {                              /* Set SMC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t SCESM:6;
      vuint32_t  :10;
      vuint32_t SOWSM:6;
      vuint32_t  :2;
      vuint32_t SNVSM:6;
    } B;
  } CH0_SSESR;

  union {                              /* Sync Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t STSV:24;
    } B;
  } CH0_STSRR;

  union {                              /* Data Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t SLOT_COUNTER:3;
      vuint32_t DTSV:24;
    } B;
  } CH0_DTSRR;

  union {                              /* Slot n Frame Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_EN:1;
      vuint32_t TS_CAPT:1;
      vuint32_t  :1;
      vuint32_t SMCL:1;
      vuint32_t  :9;
      vuint32_t DRL:5;
      vuint32_t CRCP:1;
    } B;
  } CH0_SFCR[6];

  union {                              /* Slot 1 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S1SBT:15;
    } B;
  } CH0_S1SBR;

  union {                              /* Slot 2 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S2SBT:15;
    } B;
  } CH0_S2SBR;

  union {                              /* Slot 3 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S3SBT:15;
    } B;
  } CH0_S3SBR;

  union {                              /* Slot 4 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S4SBT:15;
    } B;
  } CH0_S4SBR;

  union {                              /* Slot 5 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S5SBT:15;
    } B;
  } CH0_S5SBR;

  union {                              /* Slot 6 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S6SBT:15;
    } B;
  } CH0_S6SBR;

  union {                              /* Slot n End Boundary Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_NO:3;
      vuint32_t  :1;
      vuint32_t SnEBT:15;
    } B;
  } CH0_SnEBR;

  union {                              /* Data Output Block Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t DATA_LENGTH:6;
      vuint16_t DBR_RST:1;
      vuint16_t DSR_RST:1;
      vuint16_t CMD_TYPE:3;
      vuint16_t DEFAULT_SYNC:1;
      vuint16_t GTM_TRIG_SEL:1;
      vuint16_t SP_PULSE_SEL:1;
      vuint16_t OP_SEL:1;
      vuint16_t SW_READY:1;
    } B;
  } CH0_DOBCR;

  union {                              /* Manchestor Decoder Disable Offset */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t MDDIS_OFF:7;
    } B;
  } CH0_MDDIS_OFF;

  union {                              /* Pulse Width for Data Bit Value 0 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width0:7;
    } B;
  } CH0_PW0D;

  union {                              /* Pulse Width for Data Bit Value 1 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width1:7;
    } B;
  } CH0_PW1D;

  union {                              /* Counter Target Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CTPR:16;
    } B;
  } CH0_CTPR;

  union {                              /* Counter Initialize Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CIPR:16;
    } B;
  } CH0_CIPR;

  union {                              /* Data Preparation Register Low */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DPR:24;
    } B;
  } CH0_DPRL;

  union {                              /* Data Preparation Register High */
    vuint32_t R;
    struct {
      vuint32_t  :32;
    } B;
  } CH0_DPRH;

  union {                              /* Data Buffer Register Low */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH0_DBRL;

  union {                              /* Data Buffer Register High */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH0_DBRH;

  union {                              /* Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH0_DSRL;

  union {                              /* Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH0_DSRH;

  uint8_t PSI5_reserved1[4];
  union {                              /* PSI5 Channel Control Register */
    vuint32_t R;
    struct {
      vuint32_t CTC_GED_SEL:1;
      vuint32_t CTC_ED:1;
      vuint32_t  :1;
      vuint32_t MEM_DEPTH:5;
      vuint32_t  :3;
      vuint32_t ERROR_SELECT4:1;
      vuint32_t ERROR_SELECT3:1;
      vuint32_t ERROR_SELECT2:1;
      vuint32_t ERROR_SELECT1:1;
      vuint32_t ERROR_SELECT0:1;
      vuint32_t  :1;
      vuint32_t GTM_RESET_ASYNC_EN:1;
      vuint32_t  :3;
      vuint32_t DEBUG_EN:1;
      vuint32_t DEBUG_FREEZE_CTRL:1;
      vuint32_t SP_TS_CLK_SEL:1;
      vuint32_t  :2;
      vuint32_t FAST_CLR_SMC:1;
      vuint32_t FAST_CLR_PSI5:1;
      vuint32_t BIT_RATE:1;
      vuint32_t MODE:1;
      vuint32_t PSI5_CH_CONFIG:1;
      vuint32_t PSI5_CH_EN:1;
    } B;
  } CH1_PCCR;

  union {                              /* DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t DMA_PM_DS_WM:5;
      vuint32_t  :5;
      vuint32_t IE_DMA_TF_SF:1;
      vuint32_t IE_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IE_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IE_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IE_DMA_PM_DS_UF:1;
      vuint32_t  :5;
      vuint32_t DMA_EN_SF:1;
      vuint32_t DMA_PM_DS_CONFIG:2;
    } B;
  } CH1_DCR;

  union {                              /* DMA Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t IS_DMA_TF_SF:1;
      vuint32_t IS_DMA_TF_PM_DS:1;
      vuint32_t  :5;
      vuint32_t IS_DMA_PM_DS_FIFO_FULL:1;
      vuint32_t IS_DMA_SFUF:1;
      vuint32_t  :1;
      vuint32_t IS_DMA_PM_DS_UF:1;
      vuint32_t  :8;
    } B;
  } CH1_DSR;

  union {                              /* General Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t IE_CESM:6;
      vuint32_t IE_STS:1;
      vuint32_t IE_DTS:1;
      vuint32_t IE_DSROW:1;
      vuint32_t IE_BROW:1;
      vuint32_t IE_PROW:1;
      vuint32_t IE_DSRR:1;
      vuint32_t IE_BRR:1;
      vuint32_t IE_PRR:1;
      vuint32_t  :2;
      vuint32_t IE_OWSM:6;
      vuint32_t  :2;
      vuint32_t IE_NVSM:6;
    } B;
  } CH1_GICR;

  union {                              /* New Data Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ND:32;
    } B;
  } CH1_NDICR;

  union {                              /* Overwrite Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_OW:32;
    } B;
  } CH1_OWICR;

  union {                              /* Error Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t IE_ERROR:32;
    } B;
  } CH1_EICR;

  union {                              /* General Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t IS_DB_FR:1;
      vuint32_t  :1;
      vuint32_t IS_CESM:6;
      vuint32_t IS_STS:1;
      vuint32_t IS_DTS:1;
      vuint32_t IS_DSROW:1;
      vuint32_t IS_BROW:1;
      vuint32_t IS_PROW:1;
      vuint32_t DSR_RDY:1;
      vuint32_t DBR_RDY:1;
      vuint32_t DPR_RDY:1;
      vuint32_t  :2;
      vuint32_t IS_OWSM:6;
      vuint32_t  :2;
      vuint32_t IS_NVSM:6;
    } B;
  } CH1_GISR;

  union {                              /* DMA PSI5 Message Register */
    vuint32_t R;
    struct {
      vuint32_t PSI5_RXDATA:32;
    } B;
  } CH1_DPMR;

  union {                              /* DMA SMC Frame Register */
    vuint32_t R;
    struct {
      vuint32_t SMC_RXDATA:32;
    } B;
  } CH1_DSFR;

  union {                              /* DMA Diagnostic Status Register */
    vuint32_t R;
    struct {
      vuint32_t DDS:32;
    } B;
  } CH1_DDSR;

  union {                              /* PSI5 Message Receive Register Low */
    vuint32_t R;
    struct {
      vuint32_t DATA_REGION:28;
      vuint32_t CRC:3;
      vuint32_t C:1;
    } B;
  } CH1_PMRRL;

  union {                              /* PSI5 Message Receive Register High */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t F:1;
      vuint32_t EM:1;
      vuint32_t E:1;
      vuint32_t T:1;
      vuint32_t SlotCounter:3;
      vuint32_t TimeStampValue:24;
    } B;
  } CH1_PMRRH;

  struct {
    union {                            /* PSI5 Message Register Low i */
      vuint32_t R;
      struct {
        vuint32_t DATA_REGION:28;
        vuint32_t CRCP:3;
        vuint32_t C:1;
      } B;
    } PMRL;
    union {                            /* PSI5 Message Register High i */
      vuint32_t R;
      struct {
        vuint32_t O:1;
        vuint32_t F:1;
        vuint32_t EM:1;
        vuint32_t E:1;
        vuint32_t T:1;
        vuint32_t Slot_Counter:3;
        vuint32_t TimeStampValue:24;
      } B;
    } PMRH;
  } CH1[32];

  union {                              /* SMC Frame Register n */
    vuint32_t R;
    struct {
      vuint32_t SLOT_NO:3;
      vuint32_t CER:1;
      vuint32_t OW:1;
      vuint32_t CRC:6;
      vuint32_t C:1;
      vuint32_t ID:4;
      vuint32_t IDDATA:4;
      vuint32_t DATA:12;
    } B;
  } CH1_SFR[6];

  union {                              /* New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t NDS:32;
    } B;
  } CH1_NDSR;

  union {                              /* Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t OWS:32;
    } B;
  } CH1_OWSR;

  union {                              /* Error Indication Status Register */
    vuint32_t R;
    struct {
      vuint32_t ERROR:32;
    } B;
  } CH1_EISR;

  union {                              /* Set New Data Status Register */
    vuint32_t R;
    struct {
      vuint32_t SNDS:32;
    } B;
  } CH1_SNDSR;

  union {                              /* Set Overwrite Status Register */
    vuint32_t R;
    struct {
      vuint32_t SOWS:32;
    } B;
  } CH1_SOWSR;

  union {                              /* Set Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t SERROR:32;
    } B;
  } CH1_SEISR;

  union {                              /* Set SMC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t SCESM:6;
      vuint32_t  :10;
      vuint32_t SOWSM:6;
      vuint32_t  :2;
      vuint32_t SNVSM:6;
    } B;
  } CH1_SSESR;

  union {                              /* Sync Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t STSV:24;
    } B;
  } CH1_STSRR;

  union {                              /* Data Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t SLOT_COUNTER:3;
      vuint32_t DTSV:24;
    } B;
  } CH1_DTSRR;

  union {                              /* Slot n Frame Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_EN:1;             /* SLOT_EN */
      vuint32_t TS_CAPT:1;             /* TS_CAPT */
      vuint32_t  :1;
      vuint32_t SMCL:1;
      vuint32_t  :9;
      vuint32_t DRL:5;
      vuint32_t CRCP:1;                /* CRCP */
    } B;
  } CH1_SFCR[6];

  union {                              /* Slot 1 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S1SBT:15;
    } B;
  } CH1_S1SBR;

  union {                              /* Slot 2 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S2SBT:15;
    } B;
  } CH1_S2SBR;

  union {                              /* Slot 3 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S3SBT:15;
    } B;
  } CH1_S3SBR;

  union {                              /* Slot 4 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S4SBT:15;
    } B;
  } CH1_S4SBR;

  union {                              /* Slot 5 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S5SBT:15;
    } B;
  } CH1_S5SBR;

  union {                              /* Slot 6 Start Boundary Register */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t S6SBT:15;
    } B;
  } CH1_S6SBR;

  union {                              /* Slot n End Boundary Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t SLOT_NO:3;
      vuint32_t  :1;
      vuint32_t SnEBT:15;
    } B;
  } CH1_SnEBR;

  union {                              /* Data Output Block Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t DATA_LENGTH:6;
      vuint16_t DBR_RST:1;
      vuint16_t DSR_RST:1;
      vuint16_t CMD_TYPE:3;
      vuint16_t DEFAULT_SYNC:1;
      vuint16_t GTM_TRIG_SEL:1;
      vuint16_t SP_PULSE_SEL:1;
      vuint16_t OP_SEL:1;
      vuint16_t SW_READY:1;
    } B;
  } CH1_DOBCR;

  union {                              /* Manchestor Decoder Disable Offset */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t MDDIS_OFF:7;
    } B;
  } CH1_MDDIS_OFF;

  union {                              /* Pulse Width for Data Bit Value 0 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width0:7;
    } B;
  } CH1_PW0D;

  union {                              /* Pulse Width for Data Bit Value 1 */
    vuint16_t R;
    struct {
      vuint16_t  :9;
      vuint16_t Pulse_Width1:7;
    } B;
  } CH1_PW1D;

  union {                              /* Counter Target Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CTPR:16;
    } B;
  } CH1_CTPR;

  union {                              /* Counter Initialize Pulse Register */
    vuint16_t R;
    struct {
      vuint16_t CIPR:16;
    } B;
  } CH1_CIPR;

  union {                              /* Data Preparation Register Low */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DPR:24;
    } B;
  } CH1_DPRL;

  union {                              /* Data Preparation Register High */
    vuint32_t R;
    struct {
      vuint32_t  :32;
    } B;
  } CH1_DPRH;

  union {                              /* Data Buffer Register Low */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH1_DBRL;

  union {                              /* Data Buffer Register High */
    vuint32_t R;
    struct {
      vuint32_t DBR:32;
    } B;
  } CH1_DBRH;

  union {                              /* Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH1_DSRL;

  union {                              /* Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t DSR:32;
    } B;
  } CH1_DSRH;
};


/* ============================================================================
   =============================== Module: PSI5S ==============================
   ============================================================================ */

struct PSI5S_tag {
  union {                              /* PSI5-S LIN Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :19;
      vuint32_t AUTOWU:1;
      vuint32_t  :4;
      vuint32_t  :1;
      vuint32_t SLFM:1;
      vuint32_t LBKM:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t RBLM:1;
      vuint32_t SLEEP:1;
      vuint32_t INIT:1;
    } B;
  } LINCR1;

  union {                              /* PSI5-S LIN Interrupt enable register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZIE:1;
      vuint32_t OCIE:1;
      vuint32_t  :5;
      vuint32_t FEIE:1;
      vuint32_t BOIE:1;
      vuint32_t  :1;
      vuint32_t WUIE:1;
      vuint32_t  :1;
      vuint32_t TOIE:1;
      vuint32_t DRIE:1;
      vuint32_t DTIE:1;
      vuint32_t  :1;
    } B;
  } LINIER;

  union {                              /* PSI5-S LIN Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t LINS3:1;
      vuint32_t LINS2:1;
      vuint32_t LINS1:1;
      vuint32_t LINS0:1;
      vuint32_t  :5;
      vuint32_t  :1;
      vuint32_t  :6;
    } B;
  } LINSR;

  uint8_t PSI5S_reserved0[4];
  union {                              /* PSI5-S UART Mode Control Register */
    vuint32_t R;
    struct {
      vuint32_t MIS:1;
      vuint32_t CSP:3;
      vuint32_t OSR:4;
      vuint32_t ROSE:1;
      vuint32_t NEF:3;
      vuint32_t PCE_TXDTU:1;
      vuint32_t SBUR:2;
      vuint32_t WLS:1;
      vuint32_t TDFLTFC:3;
      vuint32_t RDFLRFC:3;
      vuint32_t RFBM:1;
      vuint32_t TFBM:1;
      vuint32_t WL1:1;
      vuint32_t PC1:1;
      vuint32_t RxEn:1;
      vuint32_t TxEn:1;
      vuint32_t PC0:1;
      vuint32_t PCE_Rx:1;
      vuint32_t WL0:1;
      vuint32_t UART:1;
    } B;
  } UARTCR;

  union {                              /* PSI5-S UART Mode Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SZF:1;
      vuint32_t OCF:1;
      vuint32_t PE3:1;
      vuint32_t PE2:1;
      vuint32_t PE1:1;
      vuint32_t PE0:1;
      vuint32_t RMB:1;
      vuint32_t FEF:1;
      vuint32_t BOF:1;
      vuint32_t RDI:1;
      vuint32_t WUF:1;
      vuint32_t RFNE:1;
      vuint32_t TO:1;
      vuint32_t DRF:1;
      vuint32_t DTF:1;
      vuint32_t NF:1;
    } B;
  } UARTSR;

  uint8_t PSI5S_reserved1[12];
  union {                              /* PSI5-S LIN Fractional Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t FBR:4;
    } B;
  } LINFBRR;

  union {                              /* PSI5-S LIN Integer Baud Rate Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t IBR:20;
    } B;
  } LINIBRR;

  uint8_t PSI5S_reserved2[4];
  union {                              /* PSI5-S LIN Control Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :17;
      vuint32_t  :1;
      vuint32_t  :4;
      vuint32_t ABRQ:1;
      vuint32_t  :9;
    } B;
  } LINCR2;

  uint8_t PSI5S_reserved3[4];
  union {                              /* PSI5-S Buffer Data Register Least Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA_TX3:8;
      vuint32_t DATA_TX2:8;
      vuint32_t DATA_TX1:8;
      vuint32_t DATA_TX0:8;
    } B;
  } BDRL;

  union {                              /* PSI5-S Buffer Data Register Most Significant */
    vuint32_t R;
    struct {
      vuint32_t DATA_RX3:8;
      vuint32_t DATA_RX2:8;
      vuint32_t DATA_RX1:8;
      vuint32_t DATA_RX0:8;
    } B;
  } BDRM;

  uint8_t PSI5S_reserved4[12];
  union {                              /* PSI5-S Global Control register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TDFBM:1;
      vuint32_t RDFBM:1;
      vuint32_t TDLIS:1;
      vuint32_t RDLIS:1;
      vuint32_t STOP:1;
      vuint32_t SR:1;
    } B;
  } GCR;

  union {                              /* PSI5-S UART Preset Timeout Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t PTO:12;
    } B;
  } UARTPTO;

  union {                              /* UPSI5-S ART Current Timeout register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t CTO:12;
    } B;
  } UARTCTO;

  union {                              /* DMA Tx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t DTE0:1;
    } B;
  } DMATXE;

  union {                              /* DMA Rx Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t DRE0:1;
    } B;
  } DMARXE;

  union {                              /* PSI5-S UART Tx Idle Delay Time Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t IFD:5;
      vuint32_t EN:1;
    } B;
  } PTD;

  uint8_t PSI5S_reserved5[80];
  union {                              /* PSI5-S Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t DIRCMD_LEN:2;
      vuint32_t  :1;
      vuint32_t IE_DIRCMD_RDY:1;
      vuint32_t  :1;
      vuint32_t DEBUG_EN:1;
      vuint32_t GTM_TRIG_SEL:2;
      vuint32_t GL_DDSR_TRIG:1;
      vuint32_t GL_MODETR_DONE_EN:1;
      vuint32_t MRU_ERR_EN:1;
      vuint32_t TSCS_B:1;
      vuint32_t TSCS_A:1;
      vuint32_t CLR_CNTR_B:1;
      vuint32_t CLR_CNTR_A:1;
      vuint32_t CLRTSCNT_G:1;
      vuint32_t CLRTSCNT_G_L:1;
      vuint32_t TSCNT_EN_B:1;
      vuint32_t TSCNT_EN_A:1;
      vuint32_t TSCNTEN_G:1;
      vuint32_t TSCNTEN_G_L:1;
      vuint32_t GLOBAL_MODE:3;
    } B;
  } GLCR;

  union {                              /* PSI5-S Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t DIRCMD_RDY:1;
      vuint32_t  :4;
      vuint32_t GL_MODETR_DONE:1;
      vuint32_t MRU_ERR:1;
      vuint32_t  :7;
      vuint32_t FID:3;
      vuint32_t CHID:3;
    } B;
  } GLSR;

  union {                              /* PSI5-S CHANNEL_BASE_ADDRESS */
    vuint32_t R;
    struct {
      vuint32_t MAILBOX_BASE_ADDR:32;
    } B;
  } CH_BASE_ADDR;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER0 */
    vuint32_t R;
    struct {
      vuint32_t CHANNEL_SPECIFIC_MAILBOX_ADDR:32;
    } B;
  } MRU_BUF2_REG0;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER1 */
    vuint32_t R;
    struct {
      vuint32_t DCI:4;
      vuint32_t  :1;
      vuint32_t R_UVL_ERR:1;
      vuint32_t N_ERR:1;
      vuint32_t CHID:3;
      vuint32_t FID:3;
      vuint32_t R_OVL_ERR:1;
      vuint32_t F_WD_ERR:1;
      vuint32_t SCI_O_ERR:1;
      vuint32_t SCI_F_ERR:1;
      vuint32_t SCI_P_ERR:1;
      vuint32_t HD_ERR:1;
      vuint32_t ERR:2;
      vuint32_t CRC_ERR_P_ERR:1;
      vuint32_t CRC:3;
      vuint32_t XCRC_ERR:1;
      vuint32_t XCRC:6;
    } B;
  } MRU_BUF2_REG1;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER2 */
    vuint32_t R;
    struct {
      vuint32_t DCI:4;
      vuint32_t PS_DATA:28;
    } B;
  } MRU_BUF2_REG2;

  union {                              /* PSI5-S MRU OUTPUT BUFFER2 REGISTER3 */
    vuint32_t R;
    struct {
      vuint32_t DCI:4;
      vuint32_t  :4;
      vuint32_t TIMESTAMP:24;
    } B;
  } MRU_BUF2_REG3;

  union {                              /* PSI5-S Clock Divider "0" for WatchDog and DownStream Data Shift Register Trigger Counters . Used for Channel1 and Channel2 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV0:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV0:10;
    } B;
  } WD_DDTRIG_CLKDIV0;

  union {                              /* PSI5-S Clock Divider "1" for WatchDog and DownStream Data Shift Register Trigger Counters . Used for Channel3 and Channel4 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV1:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV1:10;
    } B;
  } WD_DDTRIG_CLKDIV1;

  union {                              /* PSI5-S Clock Divider "2" for WatchDog and DownStream Data Shift Register Trigger Counters . Used for Channel5 and Channel6 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV2:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV2:10;
    } B;
  } WD_DDTRIG_CLKDIV2;

  union {                              /* PSI5-S Clock Divider "3" for WatchDog and DownStream Data Shift Register Trigger Counters . Used for Channel7 */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t WD_CLKDIV3:10;
      vuint32_t  :6;
      vuint32_t DDTRIG_CLKDIV3:10;
    } B;
  } WD_DDTRIG_CLKDIV3;

  union {                              /* PSI5-S Mbox Status Irq */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t MBOX_CH7:1;
      vuint32_t MBOX_CH6:1;
      vuint32_t MBOX_CH5:1;
      vuint32_t MBOX_CH4:1;
      vuint32_t MBOX_CH3:1;
      vuint32_t MBOX_CH2:1;
      vuint32_t MBOX_CH1:1;
      vuint32_t MBOX_CH0:1;
    } B;
  } MBOX_SR_IRQ;

  union {                              /* PSI5-S Error Status Irq */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t R_UVL_ERR:1;
      vuint32_t N_ERR:1;
      vuint32_t R_OVL_ERR:1;
      vuint32_t F_WD_ERR:1;
      vuint32_t SCI_O_ERR:1;
      vuint32_t SCI_F_ERR:1;
      vuint32_t SCI_P_ERR:1;
      vuint32_t HD_ERR:1;
      vuint32_t CRC_ERR_P_ERR:1;
      vuint32_t XCRC_ERR:1;
    } B;
  } ERR_SR_IRQ;

  struct {
    union {                            /* PSI5-S Mailbox select IRQ[irq_n] */
      vuint32_t R;
      struct {
        vuint32_t  :24;
        vuint32_t MBOX_CH7_SEL:1;
        vuint32_t MBOX_CH6_SEL:1;
        vuint32_t MBOX_CH5_SEL:1;
        vuint32_t MBOX_CH4_SEL:1;
        vuint32_t MBOX_CH3_SEL:1;
        vuint32_t MBOX_CH2_SEL:1;
        vuint32_t MBOX_CH1_SEL:1;
        vuint32_t MBOX_CH0_SEL:1;
      } B;
    } MBOX;
    union {                            /* PSI5-S Error Select IRQ[iq_n] */
      vuint32_t R;
      struct {
        vuint32_t  :22;
        vuint32_t R_UVL_ERR_SEL:1;
        vuint32_t N_ERR_SEL:1;
        vuint32_t R_OVL_ERR_SEL:1;
        vuint32_t F_WD_ERR_SEL:1;
        vuint32_t SCI_O_ERR_SEL:1;
        vuint32_t SCI_F_ERR_SEL:1;
        vuint32_t SCI_P_ERR_SEL:1;
        vuint32_t HD_ERR_SEL:1;
        vuint32_t CRC_ERR_SEL:1;
        vuint32_t XCRC_ERR_SEL:1;
      } B;
    } ERR;
  } SEL_IRQ[8];

  union {                              /* PSI5-S Watchdog Error Status and Watchdog Timestamp status register */
    vuint32_t R;
    struct {
      vuint32_t F_WD_ERR_STATUS:7;
      vuint32_t  :1;
      vuint32_t WDTS_STATUS:24;
    } B;
  } WDGTSSR;

  uint8_t PSI5S_reserved6[64];
  union {                              /* PSI5-S channel 0 message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t F0_BYTE:3;
      vuint32_t  :2;
      vuint32_t TIMESTAMP_A_B_SEL:1;
      vuint32_t  :1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t  :2;
    } B;
  } MSGA_CH0;

  union {                              /* PSI5-S channel 0 message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH0;

  uint8_t PSI5S_reserved7[4];
  union {                              /* PSI5-S Mailbox status register channel0 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH0;

  uint8_t PSI5S_reserved8[20];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH1;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH1;

  uint8_t PSI5S_reserved9[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH1;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH1;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH1;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH1;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH1;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH1;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH1;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH1;

  uint8_t PSI5S_reserved10[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH2;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH2;

  uint8_t PSI5S_reserved11[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH2;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH2;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH2;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH2;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH2;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH2;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH2;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH2;

  uint8_t PSI5S_reserved12[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH3;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH3;

  uint8_t PSI5S_reserved13[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH3;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH3;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH3;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH3;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH3;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH3;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH3;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH3;

  uint8_t PSI5S_reserved14[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH4;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH4;

  uint8_t PSI5S_reserved15[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH4;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH4;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH4;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH4;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH4;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH4;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH4;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH4;

  uint8_t PSI5S_reserved16[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH5;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH5;

  uint8_t PSI5S_reserved17[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH5;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH5;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH5;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH5;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH5;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH5;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH5;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH5;

  uint8_t PSI5S_reserved18[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH6;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH6;

  uint8_t PSI5S_reserved19[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH6;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH6;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH6;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH6;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH6;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH6;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH6;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH6;

  uint8_t PSI5S_reserved20[16];
  union {                              /* PSI5-S channel message configuration register A */
    vuint32_t R;
    struct {
      vuint32_t L_PC_EN:1;
      vuint32_t F5_BYTE:3;
      vuint32_t L_PC5:1;
      vuint32_t F4_BYTE:3;
      vuint32_t L_PC4:1;
      vuint32_t F3_BYTE:3;
      vuint32_t L_PC3:1;
      vuint32_t F2_BYTE:3;
      vuint32_t L_PC2:1;
      vuint32_t F1_BYTE:3;
      vuint32_t L_PC1:1;
      vuint32_t F0_BYTE:3;
      vuint32_t L_PC0:1;
      vuint32_t MODE:1;
      vuint32_t TIME_STAMP_A_B_SEL:1;
      vuint32_t TMSG_TCMD:1;
      vuint32_t TSBUF_CLR:1;
      vuint32_t TSBUF_EN:1;
      vuint32_t G_PC:1;
      vuint32_t CH_EN:1;
    } B;
  } MSGA_CH7;

  union {                              /* PSI5-S channel message configuration register B */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t F5_payload:5;
      vuint32_t F4_payload:5;
      vuint32_t F3_payload:5;
      vuint32_t F2_payload:5;
      vuint32_t F1_payload:5;
      vuint32_t F0_payload:5;
    } B;
  } MSGB_CH7;

  uint8_t PSI5S_reserved21[4];
  union {                              /* PSI5-S Mailbox status register channel */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t F5_ERR:1;
      vuint32_t F5_OV:1;
      vuint32_t F5_READ:1;
      vuint32_t F4_ERR:1;
      vuint32_t F4_OV:1;
      vuint32_t F4_READ:1;
      vuint32_t F3_ERR:1;
      vuint32_t F3_OV:1;
      vuint32_t F3_READ:1;
      vuint32_t F2_ERR:1;
      vuint32_t F2_OV:1;
      vuint32_t F2_READ:1;
      vuint32_t F1_ERR:1;
      vuint32_t F1_OV:1;
      vuint32_t F1_READ:1;
      vuint32_t F0_ERR:1;
      vuint32_t F0_OV:1;
      vuint32_t F0_READ:1;
    } B;
  } MBOX_SR_CH7;

  union {                              /* PSI5-S channel watchdog configuration register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t WDRST:1;
      vuint32_t WDCS:1;
      vuint32_t WDEN:1;
      vuint32_t  :1;
      vuint32_t WD_TO:24;
    } B;
  } WD_CFGR_CH7;

  union {                              /* PSI5-S DDSR Trigger offset register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_OFFR:16;
    } B;
  } DDTRIG_OFFR_CH7;

  union {                              /* PSI5-S DDSR Trigger period register channel */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t DDTRIG_PERR:16;
    } B;
  } DDTRIG_PERR_CH7;

  union {                              /* PSI5-S ECU to Sensor Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t CMD:5;
      vuint32_t  :1;
      vuint32_t ACMD:5;
      vuint32_t  :2;
      vuint32_t CH_TRIG:1;
      vuint32_t GL_TRIG_SEL:1;
      vuint32_t DEFAULT_SYNC:1;
      vuint32_t DDSR_SHIFT_SEL:1;
      vuint32_t DDSR_CLR:1;
      vuint32_t DDSR_CLK_SEL:1;
      vuint32_t CMDTR_SW_CTRL:1;
      vuint32_t  :1;
      vuint32_t SYNCHRO_OVF_IE:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT_IE:1;
      vuint32_t CMDPR_BZY_IE:1;
      vuint32_t DDSR_RDY_IE:1;
      vuint32_t  :2;
      vuint32_t CMD_TYPE:3;
    } B;
  } E2SCR_CH7;

  union {                              /* PSI5-S ECU to Sensor Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t SYCHRO_OVF:1;
      vuint32_t  :1;
      vuint32_t CMDTR_NWRT:1;
      vuint32_t CMDPR_BZY:1;
      vuint32_t DDSR_RDY:1;
      vuint32_t  :5;
    } B;
  } E2SSR_CH7;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register High */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t DDSR_H:11;
    } B;
  } DDSR_H_CH7;

  union {                              /* PSI5-S channel1 ECU to Sensor Downstream Data Shift Register Low */
    vuint32_t R;
    struct {
      vuint32_t DDSR_L1:8;
      vuint32_t DDSR_L2:24;
    } B;
  } DDSR_L_CH7;
};


/* ============================================================================
   =============================== Module: REG_PROT ===========================
   ============================================================================ */

struct REG_PROT_tag {
  uint8_t REG_PROT_reserved0[14336];
  union {                              /* Soft Lock Bit Register n */
    vuint8_t R;
    struct {
      vuint8_t WE0:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t WE1:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t WE2:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t WE3:1;                  /* Write Enable Bits for Soft Lock Bits (SLB) */
      vuint8_t SLB0:1;                 /* Soft Lock Bits for one MRn register */
      vuint8_t SLB1:1;                 /* Soft Lock Bits for one MRn register */
      vuint8_t SLB2:1;                 /* Soft Lock Bits for one MRn register */
      vuint8_t SLB3:1;                 /* Soft Lock Bits for one MRn register */
    } B;
  } SLBRn;

  uint8_t REG_PROT_reserved1[2043];
  union {                              /* Global Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t HLB:1;                 /* Hard Lock Bit */
      vuint32_t  :7;
      vuint32_t UAA:1;                 /* User Access Allowed. */
      vuint32_t  :23;
    } B;
  } GCR;
};


/* ============================================================================
   =============================== Module: SARADC =============================
   ============================================================================ */

struct SARADC_tag {
  union {                              /* Main Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t OWREN:1;
      vuint32_t WLSIDE:1;
      vuint32_t MODE:1;
      vuint32_t  :1;
      vuint32_t NSTART:1;
      vuint32_t NTRGEN:1;
      vuint32_t NEDGESEL:2;
      vuint32_t JSTART:1;
      vuint32_t JTRGEN:1;
      vuint32_t JEDGESEL:2;
      vuint32_t JTRGSEQ:1;
      vuint32_t  :1;
      vuint32_t  :2;
      vuint32_t WTRIGOUT:1;
      vuint32_t  :3;
      vuint32_t JTRGSEL:4;
      vuint32_t ABORTCHAIN:1;
      vuint32_t ABORT:1;
      vuint32_t  :1;
      vuint32_t FRZ:1;
      vuint32_t  :2;
      vuint32_t EDCSELF:1;
      vuint32_t PWDN:1;
    } B;
  } MCR;

  union {                              /* Main Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t NSTART:1;
      vuint32_t  :3;
      vuint32_t JSTART:1;
      vuint32_t  :4;
      vuint32_t JABORTCHAIN:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t CHADDR:8;
      vuint32_t  :5;
      vuint32_t ADCSTATUS:3;
    } B;
  } MSR;

  uint8_t SARADC_reserved0[8];
  union {                              /* Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t JEOC:1;
      vuint32_t JECH:1;
      vuint32_t EOC:1;
      vuint32_t ECH:1;
    } B;
  } ISR_STATUS;

  union {                              /* Internal channel Interrupt Pending Register */
    vuint32_t R;
    struct {
      vuint32_t EOC_CHx:32;
    } B;
  } ICIPR[3];

  union {                              /* Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t  :1;
      vuint32_t MSKJEOC:1;
      vuint32_t MSKJECH:1;
      vuint32_t MSKEOC:1;
      vuint32_t MSKECH:1;
    } B;
  } IMR;

  union {                              /* Internal Channel Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t IM_CHx:32;
    } B;
  } CIMR[3];

  union {                              /* Watchdog Threshold Interrupt Status Register */
    vuint32_t R;
    struct {
      vuint32_t WDG15H:1;
      vuint32_t WDG15L:1;
      vuint32_t WDG14H:1;
      vuint32_t WDG14L:1;
      vuint32_t WDG13H:1;
      vuint32_t WDG13L:1;
      vuint32_t WDG12H:1;
      vuint32_t WDG12L:1;
      vuint32_t WDG11H:1;
      vuint32_t WDG11L:1;
      vuint32_t WDG10H:1;
      vuint32_t WDG10L:1;
      vuint32_t WDG9H:1;
      vuint32_t WDG9L:1;
      vuint32_t WDG8H:1;
      vuint32_t WDG8L:1;
      vuint32_t WDG7H:1;
      vuint32_t WDG7L:1;
      vuint32_t WDG6H:1;
      vuint32_t WDG6L:1;
      vuint32_t WDG5H:1;
      vuint32_t WDG5L:1;
      vuint32_t WDG4H:1;
      vuint32_t WDG4L:1;
      vuint32_t WDG3H:1;
      vuint32_t WDG3L:1;
      vuint32_t WDG2H:1;
      vuint32_t WDG2L:1;
      vuint32_t WDG1H:1;
      vuint32_t WDG1L:1;
      vuint32_t WDG0H:1;
      vuint32_t WDG0L:1;
    } B;
  } WTISR;

  union {                              /* Watchdog Threshold Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t MSKWDG15H:1;
      vuint32_t MSKWDG15L:1;
      vuint32_t MSKWDG14H:1;
      vuint32_t MSKWDG14L:1;
      vuint32_t MSKWDG13H:1;
      vuint32_t MSKWDG13L:1;
      vuint32_t MSKWDG12H:1;
      vuint32_t MSKWDG12L:1;
      vuint32_t MSKWDG11H:1;
      vuint32_t MSKWDG11L:1;
      vuint32_t MSKWDG10H:1;
      vuint32_t MSKWDG10L:1;
      vuint32_t MSKWDG9H:1;
      vuint32_t MSKWDG9L:1;
      vuint32_t MSKWDG8H:1;
      vuint32_t MSKWDG8L:1;
      vuint32_t MSKWDG7H:1;
      vuint32_t MSKWDG7L:1;
      vuint32_t MSKWDG6H:1;
      vuint32_t MSKWDG6L:1;
      vuint32_t MSKWDG5H:1;
      vuint32_t MSKWDG5L:1;
      vuint32_t MSKWDG4H:1;
      vuint32_t MSKWDG4L:1;
      vuint32_t MSKWDG3H:1;
      vuint32_t MSKWDG3L:1;
      vuint32_t MSKWDG2H:1;
      vuint32_t MSKWDG2L:1;
      vuint32_t MSKWDG1H:1;
      vuint32_t MSKWDG1L:1;
      vuint32_t MSKWDG0H:1;
      vuint32_t MSKWDG0L:1;
    } B;
  } WTIMR;

  uint8_t SARADC_reserved1[8];
  union {                              /* DMA Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t DCLR:1;
      vuint32_t DMAEN:1;
    } B;
  } DMAE;

  union {                              /* Internal Channel DMA Select Register */
    vuint32_t R;
    struct {
      vuint32_t DS_CHx:32;
    } B;
  } ICDSR[3];

  uint8_t SARADC_reserved2[16];
  union {                              /* Watchdog Threshold Register */
    vuint32_t R;
    struct {
      vuint32_t  :4;
      vuint32_t THRH:12;
      vuint32_t  :4;
      vuint32_t THRL:12;
    } B;
  } WTHRHLR[4];

  uint8_t SARADC_reserved3[36];
  union {                              /* Conversion Timing Register */
    vuint32_t R;
    struct {
      vuint32_t CRES:1;
      vuint32_t  :19;
      vuint32_t PRECHG:4;
      vuint32_t INPSAMP:8;
    } B;
  } CTR[4];

  union {                              /* Internal Channel Normal Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t NCE_CHx:32;
    } B;
  } NCMR[3];

  uint8_t SARADC_reserved4[4];
  union {                              /* Internal Channel Injected Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t JCE_CH:32;
    } B;
  } ICJCMR[3];

  uint8_t SARADC_reserved5[8];
  union {                              /* Power Down Exit Delay Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t PDED:8;
    } B;
  } PDEDR;

  uint8_t SARADC_reserved6[52];
  union {                              /* Internal Channel Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t REFSEL:1;
      vuint32_t  :2;
      vuint32_t PCE:1;
      vuint32_t  :1;
      vuint32_t CTSEL:2;
      vuint32_t  :4;
      vuint32_t VALID:1;
      vuint32_t OVERW:1;
      vuint32_t RESULT:2;
      vuint32_t CDATA:16;
    } B;
  } CDR[96];

  uint8_t SARADC_reserved7[48];
  union {                              /* Internal Channel Watchdog Selection Register */
    vuint32_t R;
    struct {
      vuint32_t WSEL_CH7:4;
      vuint32_t WSEL_CH6:4;
      vuint32_t WSEL_CH5:4;
      vuint32_t WSEL_CH4:4;
      vuint32_t WSEL_CH3:4;
      vuint32_t WSEL_CH2:4;
      vuint32_t WSEL_CH1:4;
      vuint32_t WSEL_CH0:4;
    } B;
  } ICWSELR[12];

  union {                              /* Internal Channel Watchdog Enable Register */
    vuint32_t R;
    struct {
      vuint32_t WEN_CHx:32;
    } B;
  } ICWENR[3];

  uint8_t SARADC_reserved8[4];
  union {                              /* Internal Channel Analog Watchdog Out of Range register */
    vuint32_t R;
    struct {
      vuint32_t AWOR_CHx:32;
    } B;
  } ICAWORR[3];

  uint8_t SARADC_reserved9[260];
  union {                              /* Test Channel Interrupt Pending Register */
    vuint32_t R;
    struct {
      vuint32_t EOC_CHx:32;
    } B;
  } TCIPR;

  union {                              /* Test Channel Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t IM_CHx:32;
    } B;
  } TCIMR;

  union {                              /* Test Channel DMA Select Register */
    vuint32_t R;
    struct {
      vuint32_t DS_CHx:32;
    } B;
  } TCDSR;

  union {                              /* Test Channel Normal Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t NCE_CHx:32;
    } B;
  } TCNCMR;

  union {                              /* Test Channel Injected Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t JCE_CHx:32;
    } B;
  } TCJCMR;

  union {                              /* Test Channel Watchdog Selection Register */
    vuint32_t R;
    struct {
      vuint32_t WSEL_CHa:4;
      vuint32_t WSEL_CHb:4;
      vuint32_t WSEL_CHc:4;
      vuint32_t WSEL_CHd:4;
      vuint32_t WSEL_CHe:4;
      vuint32_t WSEL_CHf:4;
      vuint32_t WSEL_CHg:4;
      vuint32_t WSEL_CHh:4;
    } B;
  } TCWSELR[4];

  union {                              /* Test Channel Watchdog Enable Register */
    vuint32_t R;
    struct {
      vuint32_t WEN_CHx:32;
    } B;
  } TCWENR;

  union {                              /* Test Channel Analog Watchdog Out of Range Register */
    vuint32_t R;
    struct {
      vuint32_t AWOR_CHx:32;
    } B;
  } TCAWORR;

  uint8_t SARADC_reserved10[4];
  union {                              /* Test Channel Connection with Analog Pin Register */
    vuint32_t R;
    struct {
      vuint32_t ESIC_TCH3:1;
      vuint32_t ICSEL_TCH3:7;
      vuint32_t ESIC_TCH2:1;
      vuint32_t ICSEL_TCH2:7;
      vuint32_t ESIC_TCH1:1;
      vuint32_t ICSEL_TCH1:7;
      vuint32_t ESIC_TCH0:1;
      vuint32_t ICSEL_TCH0:7;
    } B;
  } TCCAPR[8];

  union {                              /* Test Channel Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t REFSEL:1;
      vuint32_t  :2;
      vuint32_t PCE:1;
      vuint32_t  :1;
      vuint32_t CTSEL:2;
      vuint32_t  :4;
      vuint32_t VALID:1;
      vuint32_t OVERW:1;
      vuint32_t RESULT:2;
      vuint32_t CDATA:16;
    } B;
  } TCDR[32];

  uint8_t SARADC_reserved11[48];
  union {                              /* External Channel Decode Signals Delay Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t DSD:12;
    } B;
  } DSDR;

  uint8_t SARADC_reserved12[12];
  union {                              /* External Channel Interrupt Pending Register */
    vuint32_t R;
    struct {
      vuint32_t EOC_CHx:32;
    } B;
  } ECIPR[4];

  union {                              /* External Channel Interrupt Mask Register */
    vuint32_t R;
    struct {
      vuint32_t IM_CHx:32;
    } B;
  } ECIMR[4];

  union {                              /* External Channel DMA Select Register */
    vuint32_t R;
    struct {
      vuint32_t DS_CHx:32;
    } B;
  } ECDSR[4];

  union {                              /* External Channel Normal Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t NCE_CHx:32;
    } B;
  } ECNCMR[4];

  union {                              /* External Channel Injected Conversion Mask Register */
    vuint32_t R;
    struct {
      vuint32_t JCE_CHx:32;
    } B;
  } ECJCMR[4];

  union {                              /* External Channel Watchdog Selection Register */
    vuint32_t R;
    struct {
      vuint32_t WSEL_CHa:4;
      vuint32_t WSEL_CHb:4;
      vuint32_t WSEL_CHc:4;
      vuint32_t WSEL_CHd:4;
      vuint32_t WSEL_CHe:4;
      vuint32_t WSEL_CHf:4;
      vuint32_t WSEL_CHg:4;
      vuint32_t WSEL_CHh:4;
    } B;
  } ECWSELR[16];

  union {                              /* External Channel Watchdog Enable Register */
    vuint32_t R;
    struct {
      vuint32_t WEN_CHx:32;
    } B;
  } ECWENR[4];

  union {                              /* External Channel Analog Watchdog Out of Range register */
    vuint32_t R;
    struct {
      vuint32_t AWOR_CHx:32;
    } B;
  } ECAWORR[4];

  union {                              /* External Channel Mapping to Internal Channel Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t ICSEL_ECH152_159:7;
      vuint32_t  :1;
      vuint32_t ICSEL_ECH144_151:7;
      vuint32_t  :1;
      vuint32_t ICSEL_ECH136_143:7;
      vuint32_t  :1;
      vuint32_t ICSEL_ECH128_135:7;
    } B;
  } ECMICR[4];

  union {                              /* External Channel Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t REFSEL:1;
      vuint32_t  :2;
      vuint32_t PCE:1;
      vuint32_t  :1;
      vuint32_t CTSEL:2;
      vuint32_t  :4;
      vuint32_t VALID:1;
      vuint32_t OVERW:1;
      vuint32_t RESULT:2;
      vuint32_t CDATA:16;
    } B;
  } ECDR[128];
};


/* ============================================================================
   =============================== Module: SDADC ==============================
   ============================================================================ */

struct SDADC_tag {
  union {                              /* Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :3;
      vuint32_t PDR:5;
      vuint32_t  :1;
      vuint32_t PGAN:3;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t EMSEL:1;
      vuint32_t HPFEN:1;
      vuint32_t WDGEN:1;
      vuint32_t TRIGEDSEL:2;
      vuint32_t TRIGEN:1;
      vuint32_t TRIGSEL:4;
      vuint32_t FRZ:1;
      vuint32_t  :2;
      vuint32_t VCOMSEL:1;
      vuint32_t WRMODE:1;
      vuint32_t GECEN:1;               /* Accurate Gain Error Mode Enable */
      vuint32_t MODE:1;
      vuint32_t EN:1;
    } B;
  } MCR;

  union {                              /* Channel Selection Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t BIASEN:8;
      vuint32_t  :5;
      vuint32_t ANCHSEL_WRAP:3;
      vuint32_t  :5;
      vuint32_t ANCHSEL:3;
    } B;
  } CSR;

  union {                              /* Reset Key Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t RESET_KEY:16;
    } B;
  } RKR;

  union {                              /* Status Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :13;
      vuint32_t ANCHSEL_CNT:3;
      vuint32_t  :7;
      vuint32_t DFEF:1;
      vuint32_t  :3;
      vuint32_t WTHH:1;
      vuint32_t WTHL:1;
      vuint32_t CDVF:1;
      vuint32_t DFORF:1;
      vuint32_t DFFF:1;
    } B;
  } SFR;

  union {                              /* Request Select and Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t WTHDIRS:1;
      vuint32_t DFFDIRS:1;
      vuint32_t GDIGE:1;
      vuint32_t  :11;
      vuint32_t WTHDIRE:1;
      vuint32_t CDVEE:1;
      vuint32_t DFORIE:1;
      vuint32_t DFFDIRE:1;
    } B;
  } RSER;

  uint8_t SDADC_reserved0[4];
  union {                              /* FIFO Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t FRST:1;
      vuint32_t  :3;
      vuint32_t FTHLD:5;
      vuint32_t  :4;
      vuint32_t FOWEN:1;
      vuint32_t FSIZE:2;
      vuint32_t FE:1;
    } B;
  } FCR;

  union {                              /* Software Trigger Key Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t ST_KEY:16;
    } B;
  } STKR;

  union {                              /* Converted Data Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CDATA:16;
    } B;
  } CDR;

  union {                              /* WDG Threshold Register */
    vuint32_t R;
    struct {
      vuint32_t THRH:16;
      vuint32_t THRL:16;
    } B;
  } WTHHLR;
};


/* ============================================================================
   =============================== Module: SEMA42 =============================
   ============================================================================ */

struct SEMA42_tag {
  union {                              /* Gate Register */
    vuint8_t R;
    struct {
      vuint8_t  :4;
      vuint8_t GTFSM:4;                /* [BLG_SEMA42_0001] [Covers: ADD06.057] Gate Finite State Machine. [end] */
    } B;
  } GATE[16];

  uint8_t SEMA42_reserved0[48];
  union {
    union {                            /* Reset Gate Read */
      vuint16_t R;
      struct {
        vuint16_t  :2;
        vuint16_t RSTGSM:2;
        vuint16_t RSTGMS:4;
        vuint16_t RSTGTN:8;
      } B;
    } R;
    union {                            /* Reset Gate Write */
      vuint16_t R;
      struct {
        vuint16_t RSTGDP:8;
        vuint16_t RSTGTN:8;
      } B;
    } W;
  } RSTGT;
};


/* ============================================================================
   =============================== Module: SIPI ===============================
   ============================================================================ */

struct SIPI_tag {
  union {                              /* SIPI Channel Control Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;                  /* Streaming Transfer. */
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;                 /* Read Request Transfer. */
      vuint32_t WRT:1;                 /* Write Request Transfer. */
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR0;

  union {                              /* SIPI Channel Status Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;                 /* Transaction ID of transmitted frame. */
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR0;

  uint8_t SIPI_reserved0[4];
  union {                              /* SIPI Channel Interrupt Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;                /* Write Acknowledge Interrupt Enable. */
      vuint32_t RAIE:1;                /* Read Answer Interrupt Enable. */
      vuint32_t TCIE:1;                /* Trigger Command Interrupt Enable. */
      vuint32_t TOIE:1;                /* Timeout Error Interrupt Enabled. */
      vuint32_t TIDIE:1;               /* Transaction ID Error Interrupt Enable. */
      vuint32_t ACKIE:1;               /* Acknowledge Error Interrupt Enable. */
    } B;
  } CIR0;

  union {                              /* SIPI Channel Timeout Register 0 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;                 /* Timeout value for transmitted requests. */
    } B;
  } CTOR0;

  union {                              /* SIPI Channel CRC Register 0 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC0;

  union {                              /* SIPI Channel Address Register 0 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR0;

  union {                              /* SIPI Channel Data Register 0 */
    vuint32_t R;
    struct {
      vuint32_t CDR:32;
    } B;
  } CDR0;

  union {                              /* SIPI Channel Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;
      vuint32_t WRT:1;
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR1;

  union {                              /* SIPI Channel Status Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR1;

  uint8_t SIPI_reserved1[4];
  union {                              /* SIPI Channel Interrupt Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;
      vuint32_t RAIE:1;
      vuint32_t TCIE:1;
      vuint32_t TOIE:1;
      vuint32_t TIDIE:1;
      vuint32_t ACKIE:1;
    } B;
  } CIR1;

  union {                              /* SIPI Channel Timeout Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;                 /* Timeout value for transmitted requests. */
    } B;
  } CTOR1;

  union {                              /* SIPI Channel CRC Register 1 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC1;

  union {                              /* SIPI Channel Address Register 1 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR1;

  union {                              /* SIPI Channel Data Register 1 */
    vuint32_t R;
    struct {
      vuint32_t CDR:32;
    } B;
  } CDR1;

  union {                              /* SIPI Channel Control Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;                 /* Read Request Transfer. */
      vuint32_t WRT:1;
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR2;

  union {                              /* SIPI Channel Status Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;                 /* Transaction ID of transmitted frame. */
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR2;

  uint8_t SIPI_reserved2[4];
  union {                              /* SIPI Channel Interrupt Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;
      vuint32_t RAIE:1;
      vuint32_t TCIE:1;
      vuint32_t TOIE:1;
      vuint32_t TIDIE:1;
      vuint32_t ACKIE:1;
    } B;
  } CIR2;

  union {                              /* SIPI Channel Timeout Register 2 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;
    } B;
  } CTOR2;

  union {                              /* SIPI Channel CRC Register 2 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC2;

  union {                              /* SIPI Channel Address Register 2 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR2;

  union {                              /* SIPI Channel Data Register 2 */
    vuint32_t R;
    struct {
      vuint32_t CDR2:32;
    } B;
  } CDR2[8];

  union {                              /* SIPI Channel Control Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :15;
      vuint32_t TC:1;                  /* Send Trigger Command. */
      vuint32_t  :8;
      vuint32_t WL:2;                  /* Word Length Transfer. */
      vuint32_t CHEN:1;                /* Channel Enable. */
      vuint32_t ST:1;                  /* Streaming Transfer. */
      vuint32_t IDT:1;                 /* ID Read Request Transfer. */
      vuint32_t RRT:1;
      vuint32_t WRT:1;
      vuint32_t DEN:1;                 /* DMA Enable. */
    } B;
  } CCR3;

  union {                              /* SIPI Channel Status Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t RAR:1;
      vuint32_t TID:3;                 /* Transaction ID of transmitted frame. */
      vuint32_t ACKR:1;
      vuint32_t CB:1;                  /* Channel Busy. */
      vuint32_t  :2;
    } B;
  } CSR3;

  uint8_t SIPI_reserved3[4];
  union {                              /* SIPI Channel Interrupt Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t WAIE:1;
      vuint32_t RAIE:1;
      vuint32_t TCIE:1;
      vuint32_t TOIE:1;
      vuint32_t TIDIE:1;
      vuint32_t ACKIE:1;
    } B;
  } CIR3;

  union {                              /* SIPI Channel Timeout Register 3 */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t TOR:8;                 /* Timeout value for transmitted requests. */
    } B;
  } CTOR3;

  union {                              /* SIPI Channel CRC Register 3 */
    vuint32_t R;
    struct {
      vuint32_t CRCI:16;
      vuint32_t CRCT:16;
    } B;
  } CCRC3;

  union {                              /* SIPI Channel Address Register 3 */
    vuint32_t R;
    struct {
      vuint32_t CAR:32;
    } B;
  } CAR3;

  union {                              /* SIPI Channel Data Register 3 */
    vuint32_t R;
    struct {
      vuint32_t CDR:32;
    } B;
  } CDR3;

  union {                              /* SIPI Module Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t FRZ:1;                 /* Freeze Enable */
      vuint32_t  :1;
      vuint32_t HALT:1;                /* Halt Mode Enable */
      vuint32_t  :2;
      vuint32_t PRSCLR:11;             /* Timeout counter prescaler */
      vuint32_t AID:2;                 /* Address Increment/Decrement */
      vuint32_t  :3;
      vuint32_t CRCIE:1;               /* CRC Error Interrupt Enable */
      vuint32_t MCRIE:1;               /* Max Count Reached Interrupt Enable */
      vuint32_t  :4;
      vuint32_t CHNSB:1;               /* Channel coding select bit. */
      vuint32_t TEN:1;                 /* Target Enable */
      vuint32_t INIT:1;                /* Initialization Mode */
      vuint32_t MOEN:1;                /* Module Enable */
      vuint32_t SR:1;                  /* Soft Reset */
    } B;
  } MCR;

  union {                              /* SIPI Status Register */
    vuint32_t R;
    struct {
      vuint32_t FRZACK:1;
      vuint32_t LPMACK:1;              /* Low Power Mode Acknowledge. */
      vuint32_t  :19;
      vuint32_t GCRCE:1;
      vuint32_t MCR:1;                 /* Maximum Count Reached. */
      vuint32_t  :1;
      vuint32_t TE:4;
      vuint32_t STATE:4;
    } B;
  } SR;

  union {                              /* SIPI Max Count Register */
    vuint32_t R;
    struct {
      vuint32_t MXCNT:30;
      vuint32_t  :2;
    } B;
  } MAXCR;

  union {                              /* SIPI Address Reload Register */
    vuint32_t R;
    struct {
      vuint32_t ADRLD:30;
      vuint32_t  :2;
    } B;
  } ARR;

  union {                              /* SIPI Address Count Register */
    vuint32_t R;
    struct {
      vuint32_t ADCNT:30;              /* Feflects the count value of address counter at target node. */
      vuint32_t  :2;
    } B;
  } ACR;

  union {                              /* SIPI Error Register */
    vuint32_t R;
    struct {
      vuint32_t  :5;
      vuint32_t TOE3:1;
      vuint32_t TIDE3:1;
      vuint32_t ACKE3:1;
      vuint32_t  :5;
      vuint32_t TOE2:1;
      vuint32_t TIDE2:1;
      vuint32_t ACKE2:1;
      vuint32_t  :5;
      vuint32_t TOE1:1;
      vuint32_t TIDE1:1;
      vuint32_t ACKE1:1;
      vuint32_t  :5;
      vuint32_t TOE0:1;
      vuint32_t TIDE0:1;
      vuint32_t ACKE0:1;
    } B;
  } ERR;
};


/* ============================================================================
   =============================== Module: SIUL2 ==============================
   ============================================================================ */

struct SIUL2_tag {
  uint8_t SIUL2_reserved0[4];
  union {                              /* MCU ID Register #1 */
    vuint32_t R;
    struct {
      vuint32_t PARTNUM:16;
      vuint32_t ED:1;
      vuint32_t PKG:5;
      vuint32_t  :2;
      vuint32_t MAJOR_MASK:4;
      vuint32_t MINOR_MASK:4;
    } B;
  } MIDR;

  union {                              /* MCU ID Register #2 */
    vuint32_t R;
    struct {
      vuint32_t SF:1;
      vuint32_t FLASH_SIZE_1:4;
      vuint32_t FLASH_SIZE_2:4;
      vuint32_t  :7;
      vuint32_t FAMILYNUM:8;
      vuint32_t  :8;
    } B;
  } MIDR2;

  uint8_t SIUL2_reserved1[4];
  union {                              /* DMA/Interrupt Status Flag Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t EIF11:1;
      vuint32_t EIF10:1;
      vuint32_t EIF9:1;
      vuint32_t EIF8:1;
      vuint32_t  :2;
      vuint32_t EIF5:1;
      vuint32_t EIF4:1;
      vuint32_t EIF3:1;
      vuint32_t EIF2:1;
      vuint32_t EIF1:1;
      vuint32_t EIF0:1;
    } B;
  } DISR0;

  uint8_t SIUL2_reserved2[4];
  union {                              /* DMA/Interrupt Request Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t EIRE11:1;
      vuint32_t EIRE10:1;
      vuint32_t EIRE9:1;
      vuint32_t EIRE8:1;
      vuint32_t  :2;
      vuint32_t EIRE5:1;
      vuint32_t EIRE4:1;
      vuint32_t EIRE3:1;
      vuint32_t EIRE2:1;
      vuint32_t EIRE1:1;
      vuint32_t EIRE0:1;
    } B;
  } DIRER0;

  uint8_t SIUL2_reserved3[4];
  union {                              /* DMA/Interrupt Request Select Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t DIRS11:1;
      vuint32_t DIRS10:1;
      vuint32_t DIRS9:1;
      vuint32_t DIRS8:1;
      vuint32_t  :2;
      vuint32_t DIRS5:1;
      vuint32_t DIRS4:1;
      vuint32_t DIRS3:1;
      vuint32_t DIRS2:1;
      vuint32_t DIRS1:1;
      vuint32_t DIRS0:1;
    } B;
  } DIRSR0;

  uint8_t SIUL2_reserved4[4];
  union {                              /* Interrupt Rising-Edge Event Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t IREE11:1;
      vuint32_t IREE10:1;
      vuint32_t IREE9:1;
      vuint32_t IREE8:1;
      vuint32_t  :2;
      vuint32_t IREE5:1;
      vuint32_t IREE4:1;
      vuint32_t IREE3:1;
      vuint32_t IREE2:1;
      vuint32_t IREE1:1;
      vuint32_t IREE0:1;
    } B;
  } IREER0;

  uint8_t SIUL2_reserved5[4];
  union {                              /* Interrupt Falling-Edge Event Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t IFEE11:1;
      vuint32_t IFEE10:1;
      vuint32_t IFEE9:1;
      vuint32_t IFEE8:1;
      vuint32_t  :2;
      vuint32_t IFEE5:1;
      vuint32_t IFEE4:1;
      vuint32_t IFEE3:1;
      vuint32_t IFEE2:1;
      vuint32_t IFEE1:1;
      vuint32_t IFEE0:1;
    } B;
  } IFEER0;

  uint8_t SIUL2_reserved6[4];
  union {                              /* Interrupt Filter Enable Register0 */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t IFE11:1;
      vuint32_t IFE10:1;
      vuint32_t IFE9:1;
      vuint32_t IFE8:1;
      vuint32_t  :2;
      vuint32_t IFE5:1;
      vuint32_t IFE4:1;
      vuint32_t IFE3:1;
      vuint32_t IFE2:1;
      vuint32_t IFE1:1;
      vuint32_t IFE0:1;
    } B;
  } IFER0;

  uint8_t SIUL2_reserved7[4];
  union {                              /* Interrupt Filter Maximum Counter Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t MAXCNTx:4;
    } B;
  } IFMCR[32];

  union {                              /* Interrupt Filter Clock Prescaler */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t IFCP:4;
    } B;
  } IFCPR;

  uint8_t SIUL2_reserved8[60];
  union {                              /* SoC Configuration Register0 */
    vuint32_t R;
    struct {
      vuint32_t FEC_MODE:1;
      vuint32_t  :7;
      vuint32_t ESR0_ASSERT:1;
      vuint32_t  :23;
    } B;
  } SCR0;

  uint8_t SIUL2_reserved9[316];
#if 1   //! >>>>> v1.0_issue (SIUL2): change back to MSCR[1024] <<<<<
  union {                              /* I/O Pin Multiplexed Signal Configuration Registers */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t OERC:3;
      vuint32_t  :1;
      vuint32_t ODC:3;
      vuint32_t SMC:1;
      vuint32_t APC:1;
      vuint32_t ILS:2;
      vuint32_t IBE:1;
      vuint32_t HYS:1;
      vuint32_t WPDE:1;
      vuint32_t WPUE:1;
      vuint32_t INV:1;
      vuint32_t  :7;
      vuint32_t SSS:8;
    } B;
  } MSCR[512];
#define PCR MSCR
  union {                              /* Multiplexed Signal Configuration Register for Multiplexed Input Selection */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t INV:1;
      vuint32_t  :7;
      vuint32_t SSS:8;
    } B;
  } PSMI[512];

#else

  union {                              /* I/O Pin Multiplexed Signal Configuration Registers */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t OERC:3;
      vuint32_t  :1;
      vuint32_t ODC:3;
      vuint32_t SMC:1;
      vuint32_t APC:1;
      vuint32_t ILS:2;
      vuint32_t IBE:1;
      vuint32_t HYS:1;
      vuint32_t WPDE:1;
      vuint32_t WPUE:1;
      vuint32_t INV:1;
      vuint32_t  :7;
      vuint32_t SSS:8;
    } B;
  } MSCR[1024];
#endif
  
  uint8_t SIUL2_reserved10[192];
  union {                              /* GPIO Pad Data Out Register */
    vuint8_t R;
    struct {
      vuint8_t  :7;
      vuint8_t PDO:1;
    } B;
  } GPDO[512];

  union {                              /* GPIO Pad Data In Register */
    vuint8_t R;
    struct {
      vuint8_t  :7;
      vuint8_t PDI:1;
    } B;
  } GPDI[512];

  union {                              /* Parallel GPIO Pad Data Out Register */
    vuint16_t R;
    struct {
      vuint16_t PPDO:16;
    } B;
  } PGPDO[32];

  union {                              /* Parallel GPIO Pad Data In Register */
    vuint16_t R;
    struct {
      vuint16_t PPDI:16;
    } B;
  } PGPDI[32];

  union {                              /* Masked Parallel GPIO Pad Data Out Register */
    vuint32_t R;
    struct {
      vuint32_t MASK:16;
      vuint32_t MPPDO:16;
    } B;
  } MPGPDO[32];
};


/* ============================================================================
   =============================== Module: SMPU ===============================
   ============================================================================ */

struct SMPU_tag {
  union {                              /* Control/Error Status Register 0 */
    vuint32_t R;
    struct {
      vuint32_t MERR:16;
      vuint32_t  :1;
      vuint32_t  :11;
      vuint32_t HRL:3;
      vuint32_t GVLD:1;
    } B;
  } CESR0;

  union {                              /* Control/Error Status Register 1 */
    vuint32_t R;
    struct {
      vuint32_t MEOVR:16;
      vuint32_t  :1;
      vuint32_t  :11;
      vuint32_t NRGD:4;
    } B;
  } CESR1;

  uint8_t SMPU_reserved0[248];
  struct {
    union {                            /* Error Address Register, Bus Master n */
      vuint32_t R;
      struct {
        vuint32_t EADDR:32;
      } B;
    } EAR;
    union {                            /* Error Detail Register, Bus Master n */
      vuint32_t R;
      struct {
        vuint32_t EACD:24;
        vuint32_t  :1;
        vuint32_t EATTR:2;
        vuint32_t ERW:1;
        vuint32_t EMN:4;
      } B;
    } EDR;
  } ERROR[16];

  uint8_t SMPU_reserved1[640];
  struct {
    union {                            /* Region Descriptor n, Word 0 */
      vuint32_t R;
      struct {
        vuint32_t SRTADDR:32;
      } B;
    } WORD0;
    union {                            /* Region Descriptor n, Word 1 */
      vuint32_t R;
      struct {
        vuint32_t ENDADDR:32;
      } B;
    } WORD1;
    union {                            /* Region Descriptor n, Word 2 Format 0 */
      vuint32_t R;
      struct {
        vuint32_t M0P:2;
        vuint32_t M1P:2;
        vuint32_t M2P:2;
        vuint32_t M3P:2;
        vuint32_t M4P:2;
        vuint32_t M5P:2;
        vuint32_t M6P:2;
        vuint32_t M7P:2;
        vuint32_t M8P:2;
        vuint32_t M9P:2;
        vuint32_t M10P:2;
        vuint32_t M11P:2;
        vuint32_t M12P:2;
        vuint32_t M13P:2;
        vuint32_t M14P:2;
        vuint32_t M15P:2;
      } B;
    } WORD2;
    union {                            /* Region Descriptor n, Word 3 */
      vuint32_t R;
      struct {
        vuint32_t  :27;
        vuint32_t FMT:1;
        vuint32_t RO:1;
        vuint32_t  :1;
        vuint32_t CI:1;
        vuint32_t VLD:1;
      } B;
    } WORD3;
  } RGD[12];
};


/* ============================================================================
   =============================== Module: SRX ================================
   ============================================================================ */

struct SRX_tag {
  union {                              /* Global Control Register */
    vuint32_t R;
    struct {
      vuint32_t TSPRSC:8;
      vuint32_t  :8;
      vuint32_t  :1;
      vuint32_t  :5;
      vuint32_t FMDUIE:1;
      vuint32_t SMDUIE:1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t  :1;
      vuint32_t FAST_CLR:1;
      vuint32_t  :1;
      vuint32_t DBG_FRZ:1;
      vuint32_t  :1;
      vuint32_t SENT_EN:1;
    } B;
  } GBL_CTRL;

  union {                              /* Channel Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t EN_CH:8;
    } B;
  } CHNL_EN;

  union {                              /* Global Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t FDMU:1;
      vuint32_t SMDU:1;
      vuint32_t  :8;
    } B;
  } GBL_STATUS;

  union {                              /* Fast Message Ready Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t F_RDY:8;
    } B;
  } FMSG_RDY;

  union {                              /* Slow Serial Message Ready Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t S_RDY:8;
    } B;
  } SMSG_RDY;

  uint8_t SRX_reserved0[4];
  union {                              /* Data Control Register 1 */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t NIBBCH0:3;
      vuint32_t  :1;
      vuint32_t NIBBCH1:3;
      vuint32_t  :1;
      vuint32_t NIBBCH2:3;
      vuint32_t  :1;
      vuint32_t NIBBCH3:3;
      vuint32_t  :1;
      vuint32_t NIBBCH4:3;
      vuint32_t  :1;
      vuint32_t NIBBCH5:3;
      vuint32_t  :1;
      vuint32_t NIBBCH6:3;
      vuint32_t  :1;
      vuint32_t NIBBCH7:3;
    } B;
  } DATA_CTRL1;

  uint8_t SRX_reserved1[12];
  union {                              /* Fast Message DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t FDMA_EN:8;
    } B;
  } FDMA_CTRL;

  union {                              /* Slow Serial Message DMA Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SDMA_EN:8;
    } B;
  } SDMA_CTRL;

  uint8_t SRX_reserved2[4];
  union {                              /* Fast Message Ready Interrupt Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t FRDY_IE:8;
    } B;
  } FRDY_IE;

  union {                              /* Slow Serial Message Ready Interrupt Enable Register */
    vuint32_t R;
    struct {
      vuint32_t  :24;
      vuint32_t SRDY_IE:8;
    } B;
  } SRDY_IE;

  uint8_t SRX_reserved3[4];
  union {                              /* DMA Fast Message Data Read Register */
    vuint32_t R;
    struct {
      vuint32_t CHNUM:4;
      vuint32_t SCNIB:4;
      vuint32_t DNIB1:4;
      vuint32_t DNIB2:4;
      vuint32_t DNIB3:4;
      vuint32_t DNIB4:4;
      vuint32_t DNIB5:4;
      vuint32_t DNIB6:4;
    } B;
  } DMA_FMSG_DATA;

  union {                              /* DMA Fast Message CRC Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :12;
      vuint32_t CRC4b:4;
      vuint32_t  :16;
    } B;
  } DMA_FMSG_CRC;

  union {                              /* DMA Fast Message Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t TS:32;
    } B;
  } DMA_FMSG_TS;

  uint8_t SRX_reserved4[4];
  union {                              /* DMA Slow Serial Message Bit3 Read Register */
    vuint32_t R;
    struct {
      vuint32_t CHNUM:4;
      vuint32_t TYPE:1;
      vuint32_t  :16;
      vuint32_t CFG:1;
      vuint32_t ID7_4_D3_0:4;
      vuint32_t  :1;
      vuint32_t ID3_0_DATA15_12:4;
      vuint32_t  :1;
    } B;
  } DMA_SMSG_BIT3;

  union {                              /* DMA Slow Serial Message Bit2 Read Register */
    vuint32_t R;
    struct {
      vuint32_t  :10;
      vuint32_t SMCRC:6;
      vuint32_t  :4;
      vuint32_t DATA:12;
    } B;
  } DMA_SMSG_BIT2;

  union {                              /* DMA Slow Serial Message Time Stamp Read Register */
    vuint32_t R;
    struct {
      vuint32_t TS:32;
    } B;
  } DMA_SMSG_TS;

  uint8_t SRX_reserved5[4];
  struct {
    union {                            /* Channel 'n' Clock Control Register (n = 0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t CM_PRSC:15;
        vuint32_t COMP_EN:1;
        vuint32_t  :1;
        vuint32_t PRSC:14;
      } B;
    } CLK_CTRL;
    union {                            /* Channel 'n' Status Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t BUS_IDLE:1;
        vuint32_t  :3;
        vuint32_t CAL_RESYNC:1;
        vuint32_t CAL_20_25:1;
        vuint32_t SMSG_OFLW:1;
        vuint32_t FMSG_OFLW:1;
        vuint32_t  :1;
        vuint32_t PP_DIAG_ERR:1;
        vuint32_t CAL_LEN_ERR:1;
        vuint32_t CAL_DIAG_ERR:1;
        vuint32_t NIB_VAL_ERR:1;
        vuint32_t SMSG_CRC_ERR:1;
        vuint32_t FMSG_CRC_ERR:1;
        vuint32_t NUM_EDGES_ERR:1;
        vuint32_t  :16;
      } B;
    } STATUS;
    union {                            /* Channel 'n' Configuration Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t BUS_IDLE_CNT:4;
        vuint32_t IE_CAL_RESYNC:1;
        vuint32_t IE_CAL_20_25:1;
        vuint32_t IE_SMSG_OFLW:1;
        vuint32_t IE_FMSG_OFLW:1;
        vuint32_t FCRC_CHK_OFF:1;
        vuint32_t IE_PP_DIAG_ERR:1;
        vuint32_t IE_CAL_LEN_ERR:1;
        vuint32_t IE_CAL_DIAG_ERR:1;
        vuint32_t IE_NIB_VAL_ERR:1;
        vuint32_t IE_SMSG_CRC_ERR:1;
        vuint32_t IE_FMSG_CRC_ERR:1;
        vuint32_t IE_NUM_EDGES_ERR:1;
        vuint32_t DCHNG_INT:1;
        vuint32_t CAL_RNG:1;
        vuint32_t PP_CHKSEL:1;
        vuint32_t FCRC_TYPE:1;
        vuint32_t FCRC_SC_EN:1;
        vuint32_t SCRC_TYPE:1;
        vuint32_t PAUSE_EN:1;
        vuint32_t SUCC_CAL_CHK:1;
        vuint32_t FIL_CNT:8;
      } B;
    } CONFIG;
    uint8_t CH_reserved0[4];
  } CH[8];

  uint8_t SRX_reserved6[128];
  struct {
    union {                            /* Channel 'n' Fast Message Data Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t CHNUM:4;
        vuint32_t SCNIB:4;
        vuint32_t DNIB1:4;
        vuint32_t DNIB2:4;
        vuint32_t DNIB3:4;
        vuint32_t DNIB4:4;
        vuint32_t DNIB5:4;
        vuint32_t DNIB6:4;
      } B;
    } FMSG_DATA;
    union {                            /* Channel 'n' Fast Message CRC Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :12;
        vuint32_t CRC4b:4;
        vuint32_t  :16;
      } B;
    } FMSG_CRC;
    union {                            /* Channel 'n' Fast Message Time Stamp Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t TS:32;
      } B;
    } FMSG_TS;
    union {                            /* Channel 'n' Serial Message Read Register (Bit 3) (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t CHNUM:4;
        vuint32_t TYPE:1;
        vuint32_t  :16;
        vuint32_t CFG:1;
        vuint32_t ID7_4_ID3_0:4;
        vuint32_t  :1;
        vuint32_t ID3_0_DATA15_12:4;
        vuint32_t  :1;
      } B;
    } SMSG_BIT3;
    union {                            /* Channel 'n' Serial Message Read Register (Bit 2)(n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t  :10;
        vuint32_t SMCRC:6;
        vuint32_t  :4;
        vuint32_t DATA:12;
      } B;
    } SMSG_BIT2;
    union {                            /* Channel 'n' Serial Message Time Stamp Read Register (n=0 to (CH-1)) */
      vuint32_t R;
      struct {
        vuint32_t TS:32;
      } B;
    } SMSG_TS;
  } CHANNEL[8];
};


/* ============================================================================
   =============================== Module: SSCM ===============================
   ============================================================================ */

struct SSCM_tag {
  union {                              /* SSCM System Status */
    vuint16_t R;
    struct {
      vuint16_t  :1;
      vuint16_t CER:1;                 /* Configuration Error */
      vuint16_t  :1;
      vuint16_t NXEN1:1;               /* Processor 1 Nexus enable status */
      vuint16_t NXEN:1;                /* Processor 0 Nexus enable status */
      vuint16_t  :1;
      vuint16_t  :1;
      vuint16_t  :1;
      vuint16_t BMODE:3;               /* Device Boot Mode */
      vuint16_t VLE:1;
      vuint16_t  :1;
      vuint16_t  :1;
      vuint16_t  :2;
    } B;
  } STATUS;

  union {                              /* SSCM System Memory and ID Register */
    vuint16_t R;
    struct {
      vuint16_t JPIN:10;
      vuint16_t  :1;
      vuint16_t MREV:4;                /* Minor Mask Revision */
      vuint16_t  :1;
    } B;
  } MEMCONFIG;

  uint8_t SSCM_reserved0[2];
  union {                              /* SSCM Error Configuration Register */
    vuint16_t R;
    struct {
      vuint16_t  :14;
      vuint16_t PAE:1;                 /* Peripheral Bus Abort Enable. */
      vuint16_t RAE:1;                 /* Register Bus Abort Enable. */
    } B;
  } ERROR;

  uint8_t SSCM_reserved1[24];
  union {                              /* SSCM HSM and User Option Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :28;
      vuint32_t HSB:3;                 /* HSM Boot Configuration */
      vuint32_t HSE:1;                 /* HSM Enabled */
    } B;
  } UOPS;

  uint8_t SSCM_reserved2[4];
  union {                              /* Processor Start Address Register */
    vuint32_t R;
    struct {
      vuint32_t SADR:32;               /* Processor Start Address */
    } B;
  } PSA;

  uint8_t SSCM_reserved3[4];
  union {                              /* SSCM HSM Start Address Register */
    vuint32_t R;
    struct {
      vuint32_t HADR:32;               /* HSM Start Address */
    } B;
  } HSA;

  union {                              /* Life Cycle Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t LC:3;                  /* Life Cycle */
    } B;
  } LCSTAT;
};


/* ============================================================================
   =============================== Module: STCU2 ==============================
   ============================================================================ */

struct STCU2_tag {
  union {                              /* STCU2 Run Register */
    vuint32_t R;
    struct {
      vuint32_t  :21;
      vuint32_t BYP:1;
      vuint32_t MBPLLEN:1;
      vuint32_t LBPLLEN:1;
      vuint32_t  :7;
      vuint32_t RUN:1;
    } B;
  } RUN;

  union {                              /* STCU2 Run Software Register */
    vuint32_t R;
    struct {
      vuint32_t  :20;
      vuint32_t MBIE:1;
      vuint32_t LBIE:1;
      vuint32_t MBSWPLLEN:1;
      vuint32_t LBSWPLLEN:1;
      vuint32_t  :6;
      vuint32_t RUNSW_ABORT:1;
      vuint32_t RUNSW:1;
    } B;
  } RUNSW;

  union {                              /* STCU2 SK Code Register */
    vuint32_t R;
    struct {
      vuint32_t SKC:32;
    } B;
  } SKC;

  union {                              /* STCU2 Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :1;
      vuint32_t PTR:7;
      vuint32_t LB_DELAY:8;
      vuint32_t  :7;
      vuint32_t WRP:1;
      vuint32_t  :2;
      vuint32_t CRCEN:1;
      vuint32_t PMOSEN:1;
      vuint32_t MBU:1;
      vuint32_t CLK_CFG:3;
    } B;
  } CFG;

  union {                              /* STCU2 PLL Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t  :2;
      vuint32_t PLLODF:6;
      vuint32_t  :5;
      vuint32_t PLLIDF:3;
      vuint32_t  :9;
      vuint32_t PLLLDF:7;
    } B;
  } PLL_CFG;

  union {                              /* STCU2 Watchdog Register Granularity */
    vuint32_t R;
    struct {
      vuint32_t WDGEOC:32;
    } B;
  } WDG;

  union {                              /* STCU2 Interrupt Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :30;
      vuint32_t MBIFLG:1;
      vuint32_t LBIFLG:1;
    } B;
  } INT_FLG;

  union {                              /* STCU2 CRC Expected Status Register */
    vuint32_t R;
    struct {
      vuint32_t CRCE:32;
    } B;
  } CRCE;

  union {                              /* STCU2 CRC Read Status Register */
    vuint32_t R;
    struct {
      vuint32_t CRCR:32;
    } B;
  } CRCR;

  union {                              /* STCU2 Error Register */
    vuint32_t R;
    struct {
      vuint32_t  :6;
      vuint32_t ABORTHW:1;
      vuint32_t ABORTSW:1;
      vuint32_t  :3;
      vuint32_t LOCKESW:1;
      vuint32_t WDTOSW:1;
      vuint32_t CRCSSW:1;
      vuint32_t ENGESW:1;
      vuint32_t INVPSW:1;
      vuint32_t  :6;
      vuint32_t UFSF:1;
      vuint32_t RFSF:1;
      vuint32_t  :3;
      vuint32_t LOCKE:1;
      vuint32_t WDTO:1;
      vuint32_t CRCS:1;
      vuint32_t ENGE:1;
      vuint32_t INVP:1;
    } B;
  } ERR_STAT;

  union {                              /* STCU2 Error FM Register */
    vuint32_t R;
    struct {
      vuint32_t  :27;
      vuint32_t LOCKEUFM:1;
      vuint32_t WDTOUFM:1;
      vuint32_t CRCSUFM:1;
      vuint32_t ENGEUFM:1;
      vuint32_t INVPUFM:1;
    } B;
  } ERR_FM;

  union {                              /* STCU2 Off-Line LBIST Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBS9:1;
      vuint32_t LBS8:1;
      vuint32_t LBS7:1;
      vuint32_t LBS6:1;
      vuint32_t LBS5:1;
      vuint32_t LBS4:1;
      vuint32_t LBS3:1;
      vuint32_t LBS2:1;
      vuint32_t LBS1:1;
      vuint32_t LBS0:1;
    } B;
  } LBS;

  union {                              /* STCU2 Off-Line LBIST End Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBE9:1;
      vuint32_t LBE8:1;
      vuint32_t LBE7:1;
      vuint32_t LBE6:1;
      vuint32_t LBE5:1;
      vuint32_t LBE4:1;
      vuint32_t LBE3:1;
      vuint32_t LBE2:1;
      vuint32_t LBE1:1;
      vuint32_t LBE0:1;
    } B;
  } LBE;

  union {                              /* STCU2 On-Line LBIST Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBSSW9:1;
      vuint32_t LBSSW8:1;
      vuint32_t LBSSW7:1;
      vuint32_t LBSSW6:1;
      vuint32_t LBSSW5:1;
      vuint32_t LBSSW4:1;
      vuint32_t LBSSW3:1;
      vuint32_t LBSSW2:1;
      vuint32_t LBSSW1:1;
      vuint32_t LBSSW0:1;
    } B;
  } LBSSW;

  union {                              /* STCU2 On-Line LBIST End Flag Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBESW9:1;
      vuint32_t LBESW8:1;
      vuint32_t LBESW7:1;
      vuint32_t LBESW6:1;
      vuint32_t LBESW5:1;
      vuint32_t LBESW4:1;
      vuint32_t LBESW3:1;
      vuint32_t LBESW2:1;
      vuint32_t LBESW1:1;
      vuint32_t LBESW0:1;
    } B;
  } LBESW;

  union {                              /* STCU2 On-Line LBIST Reset Management */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBRMSW9:1;
      vuint32_t LBRMSW8:1;
      vuint32_t LBRMSW7:1;
      vuint32_t LBRMSW6:1;
      vuint32_t LBRMSW5:1;
      vuint32_t LBRMSW4:1;
      vuint32_t LBRMSW3:1;
      vuint32_t LBRMSW2:1;
      vuint32_t LBRMSW1:1;
      vuint32_t LBRMSW0:1;
    } B;
  } LBRMSW;

  union {                              /* STCU2 LBIST Unrecoverable FM Register */
    vuint32_t R;
    struct {
      vuint32_t  :22;
      vuint32_t LBUFM9:1;
      vuint32_t LBUFM8:1;
      vuint32_t LBUFM7:1;
      vuint32_t LBUFM6:1;
      vuint32_t LBUFM5:1;
      vuint32_t LBUFM4:1;
      vuint32_t LBUFM3:1;
      vuint32_t LBUFM2:1;
      vuint32_t LBUFM1:1;
      vuint32_t LBUFM0:1;
    } B;
  } LBUFM;

  union {                              /* STCU2 Off-Line MBIST Status Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBS31:1;
      vuint32_t MBS30:1;
      vuint32_t MBS29:1;
      vuint32_t MBS28:1;
      vuint32_t MBS27:1;
      vuint32_t MBS26:1;
      vuint32_t MBS25:1;
      vuint32_t MBS24:1;
      vuint32_t MBS23:1;
      vuint32_t MBS22:1;
      vuint32_t MBS21:1;
      vuint32_t MBS20:1;
      vuint32_t MBS19:1;
      vuint32_t MBS18:1;
      vuint32_t MBS17:1;
      vuint32_t MBS16:1;
      vuint32_t MBS15:1;
      vuint32_t MBS14:1;
      vuint32_t MBS13:1;
      vuint32_t MBS12:1;
      vuint32_t MBS11:1;
      vuint32_t MBS10:1;
      vuint32_t MBS9:1;
      vuint32_t MBS8:1;
      vuint32_t MBS7:1;
      vuint32_t MBS6:1;
      vuint32_t MBS5:1;
      vuint32_t MBS4:1;
      vuint32_t MBS3:1;
      vuint32_t MBS2:1;
      vuint32_t MBS1:1;
      vuint32_t MBS0:1;
    } B;
  } MBSL;

  union {                              /* STCU2 Off-Line MBIST Status Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBS63:1;
      vuint32_t MBS62:1;
      vuint32_t MBS61:1;
      vuint32_t MBS60:1;
      vuint32_t MBS59:1;
      vuint32_t MBS58:1;
      vuint32_t MBS57:1;
      vuint32_t MBS56:1;
      vuint32_t MBS55:1;
      vuint32_t MBS54:1;
      vuint32_t MBS53:1;
      vuint32_t MBS52:1;
      vuint32_t MBS51:1;
      vuint32_t MBS50:1;
      vuint32_t MBS49:1;
      vuint32_t MBS48:1;
      vuint32_t MBS47:1;
      vuint32_t MBS46:1;
      vuint32_t MBS45:1;
      vuint32_t MBS44:1;
      vuint32_t MBS43:1;
      vuint32_t MBS42:1;
      vuint32_t MBS41:1;
      vuint32_t MBS40:1;
      vuint32_t MBS39:1;
      vuint32_t MBS38:1;
      vuint32_t MBS37:1;
      vuint32_t MBS36:1;
      vuint32_t MBS35:1;
      vuint32_t MBS34:1;
      vuint32_t MBS33:1;
      vuint32_t MBS32:1;
    } B;
  } MBSM;

  union {                              /* STCU2 Off-Line MBIST Status High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBS77:1;
      vuint32_t MBS76:1;
      vuint32_t MBS75:1;
      vuint32_t MBS74:1;
      vuint32_t MBS73:1;
      vuint32_t MBS72:1;
      vuint32_t MBS71:1;
      vuint32_t MBS70:1;
      vuint32_t MBS69:1;
      vuint32_t MBS68:1;
      vuint32_t MBS67:1;
      vuint32_t MBS66:1;
      vuint32_t MBS65:1;
      vuint32_t MBS64:1;
    } B;
  } MBSH;

  union {                              /* STCU2 Off-Line MBIST End Flag Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBE31:1;
      vuint32_t MBE30:1;
      vuint32_t MBE29:1;
      vuint32_t MBE28:1;
      vuint32_t MBE27:1;
      vuint32_t MBE26:1;
      vuint32_t MBE25:1;
      vuint32_t MBE24:1;
      vuint32_t MBE23:1;
      vuint32_t MBE22:1;
      vuint32_t MBE21:1;
      vuint32_t MBE20:1;
      vuint32_t MBE19:1;
      vuint32_t MBE18:1;
      vuint32_t MBE17:1;
      vuint32_t MBE16:1;
      vuint32_t MBE15:1;
      vuint32_t MBE14:1;
      vuint32_t MBE13:1;
      vuint32_t MBE12:1;
      vuint32_t MBE11:1;
      vuint32_t MBE10:1;
      vuint32_t MBE9:1;
      vuint32_t MBE8:1;
      vuint32_t MBE7:1;
      vuint32_t MBE6:1;
      vuint32_t MBE5:1;
      vuint32_t MBE4:1;
      vuint32_t MBE3:1;
      vuint32_t MBE2:1;
      vuint32_t MBE1:1;
      vuint32_t MBE0:1;
    } B;
  } MBEL;

  union {                              /* STCU2 Off-Line MBIST End Flag Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBE63:1;
      vuint32_t MBE62:1;
      vuint32_t MBE61:1;
      vuint32_t MBE60:1;
      vuint32_t MBE59:1;
      vuint32_t MBE58:1;
      vuint32_t MBE57:1;
      vuint32_t MBE56:1;
      vuint32_t MBE55:1;
      vuint32_t MBE54:1;
      vuint32_t MBE53:1;
      vuint32_t MBE52:1;
      vuint32_t MBE51:1;
      vuint32_t MBE50:1;
      vuint32_t MBE49:1;
      vuint32_t MBE48:1;
      vuint32_t MBE47:1;
      vuint32_t MBE46:1;
      vuint32_t MBE45:1;
      vuint32_t MBE44:1;
      vuint32_t MBE43:1;
      vuint32_t MBE42:1;
      vuint32_t MBE41:1;
      vuint32_t MBE40:1;
      vuint32_t MBE39:1;
      vuint32_t MBE38:1;
      vuint32_t MBE37:1;
      vuint32_t MBE36:1;
      vuint32_t MBE35:1;
      vuint32_t MBE34:1;
      vuint32_t MBE33:1;
      vuint32_t MBE32:1;
    } B;
  } MBEM;

  union {                              /* STCU2 Off-Line MBIST End Flag High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBE77:1;
      vuint32_t MBE76:1;
      vuint32_t MBE75:1;
      vuint32_t MBE74:1;
      vuint32_t MBE73:1;
      vuint32_t MBE72:1;
      vuint32_t MBE71:1;
      vuint32_t MBE70:1;
      vuint32_t MBE69:1;
      vuint32_t MBE68:1;
      vuint32_t MBE67:1;
      vuint32_t MBE66:1;
      vuint32_t MBE65:1;
      vuint32_t MBE64:1;
    } B;
  } MBEH;

  union {                              /* STCU2 On-Line MBIST Status Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBSSW31:1;
      vuint32_t MBSSW30:1;
      vuint32_t MBSSW29:1;
      vuint32_t MBSSW28:1;
      vuint32_t MBSSW27:1;
      vuint32_t MBSSW26:1;
      vuint32_t MBSSW25:1;
      vuint32_t MBSSW24:1;
      vuint32_t MBSSW23:1;
      vuint32_t MBSSW22:1;
      vuint32_t MBSSW21:1;
      vuint32_t MBSSW20:1;
      vuint32_t MBSSW19:1;
      vuint32_t MBSSW18:1;
      vuint32_t MBSSW17:1;
      vuint32_t MBSSW16:1;
      vuint32_t MBSSW15:1;
      vuint32_t MBSSW14:1;
      vuint32_t MBSSW13:1;
      vuint32_t MBSSW12:1;
      vuint32_t MBSSW11:1;
      vuint32_t MBSSW10:1;
      vuint32_t MBSSW9:1;
      vuint32_t MBSSW8:1;
      vuint32_t MBSSW7:1;
      vuint32_t MBSSW6:1;
      vuint32_t MBSSW5:1;
      vuint32_t MBSSW4:1;
      vuint32_t MBSSW3:1;
      vuint32_t MBSSW2:1;
      vuint32_t MBSSW1:1;
      vuint32_t MBSSW0:1;
    } B;
  } MBSLSW;

  union {                              /* STCU2 On-Line MBIST Status Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBSSW63:1;
      vuint32_t MBSSW62:1;
      vuint32_t MBSSW61:1;
      vuint32_t MBSSW60:1;
      vuint32_t MBSSW59:1;
      vuint32_t MBSSW58:1;
      vuint32_t MBSSW57:1;
      vuint32_t MBSSW56:1;
      vuint32_t MBSSW55:1;
      vuint32_t MBSSW54:1;
      vuint32_t MBSSW53:1;
      vuint32_t MBSSW52:1;
      vuint32_t MBSSW51:1;
      vuint32_t MBSSW50:1;
      vuint32_t MBSSW49:1;
      vuint32_t MBSSW48:1;
      vuint32_t MBSSW47:1;
      vuint32_t MBSSW46:1;
      vuint32_t MBSSW45:1;
      vuint32_t MBSSW44:1;
      vuint32_t MBSSW43:1;
      vuint32_t MBSSW42:1;
      vuint32_t MBSSW41:1;
      vuint32_t MBSSW40:1;
      vuint32_t MBSSW39:1;
      vuint32_t MBSSW38:1;
      vuint32_t MBSSW37:1;
      vuint32_t MBSSW36:1;
      vuint32_t MBSSW35:1;
      vuint32_t MBSSW34:1;
      vuint32_t MBSSW33:1;
      vuint32_t MBSSW32:1;
    } B;
  } MBSMSW;

  union {                              /* STCU2 On-Line MBIST Status High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBSSW77:1;
      vuint32_t MBSSW76:1;
      vuint32_t MBSSW75:1;
      vuint32_t MBSSW74:1;
      vuint32_t MBSSW73:1;
      vuint32_t MBSSW72:1;
      vuint32_t MBSSW71:1;
      vuint32_t MBSSW70:1;
      vuint32_t MBSSW69:1;
      vuint32_t MBSSW68:1;
      vuint32_t MBSSW67:1;
      vuint32_t MBSSW66:1;
      vuint32_t MBSSW65:1;
      vuint32_t MBSSW64:1;
    } B;
  } MBSHSW;

  union {                              /* STCU2 On-Line MBIST End Flag Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBESW31:1;
      vuint32_t MBESW30:1;
      vuint32_t MBESW29:1;
      vuint32_t MBESW28:1;
      vuint32_t MBESW27:1;
      vuint32_t MBESW26:1;
      vuint32_t MBESW25:1;
      vuint32_t MBESW24:1;
      vuint32_t MBESW23:1;
      vuint32_t MBESW22:1;
      vuint32_t MBESW21:1;
      vuint32_t MBESW20:1;
      vuint32_t MBESW19:1;
      vuint32_t MBESW18:1;
      vuint32_t MBESW17:1;
      vuint32_t MBESW16:1;
      vuint32_t MBESW15:1;
      vuint32_t MBESW14:1;
      vuint32_t MBESW13:1;
      vuint32_t MBESW12:1;
      vuint32_t MBESW11:1;
      vuint32_t MBESW10:1;
      vuint32_t MBESW9:1;
      vuint32_t MBESW8:1;
      vuint32_t MBESW7:1;
      vuint32_t MBESW6:1;
      vuint32_t MBESW5:1;
      vuint32_t MBESW4:1;
      vuint32_t MBESW3:1;
      vuint32_t MBESW2:1;
      vuint32_t MBESW1:1;
      vuint32_t MBESW0:1;
    } B;
  } MBELSW;

  union {                              /* STCU2 On-Line MBIST End Flag Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBESW63:1;
      vuint32_t MBESW62:1;
      vuint32_t MBESW61:1;
      vuint32_t MBESW60:1;
      vuint32_t MBESW59:1;
      vuint32_t MBESW58:1;
      vuint32_t MBESW57:1;
      vuint32_t MBESW56:1;
      vuint32_t MBESW55:1;
      vuint32_t MBESW54:1;
      vuint32_t MBESW53:1;
      vuint32_t MBESW52:1;
      vuint32_t MBESW51:1;
      vuint32_t MBESW50:1;
      vuint32_t MBESW49:1;
      vuint32_t MBESW48:1;
      vuint32_t MBESW47:1;
      vuint32_t MBESW46:1;
      vuint32_t MBESW45:1;
      vuint32_t MBESW44:1;
      vuint32_t MBESW43:1;
      vuint32_t MBESW42:1;
      vuint32_t MBESW41:1;
      vuint32_t MBESW40:1;
      vuint32_t MBESW39:1;
      vuint32_t MBESW38:1;
      vuint32_t MBESW37:1;
      vuint32_t MBESW36:1;
      vuint32_t MBESW35:1;
      vuint32_t MBESW34:1;
      vuint32_t MBESW33:1;
      vuint32_t MBESW32:1;
    } B;
  } MBEMSW;

  union {                              /* STCU2 On-Line MBIST End Flag High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBESW77:1;
      vuint32_t MBESW76:1;
      vuint32_t MBESW75:1;
      vuint32_t MBESW74:1;
      vuint32_t MBESW73:1;
      vuint32_t MBESW72:1;
      vuint32_t MBESW71:1;
      vuint32_t MBESW70:1;
      vuint32_t MBESW69:1;
      vuint32_t MBESW68:1;
      vuint32_t MBESW67:1;
      vuint32_t MBESW66:1;
      vuint32_t MBESW65:1;
      vuint32_t MBESW64:1;
    } B;
  } MBEHSW;

  union {                              /* STCU2 MBIST Unrecoverable FM Low Register */
    vuint32_t R;
    struct {
      vuint32_t MBUFM31:1;
      vuint32_t MBUFM30:1;
      vuint32_t MBUFM29:1;
      vuint32_t MBUFM28:1;
      vuint32_t MBUFM27:1;
      vuint32_t MBUFM26:1;
      vuint32_t MBUFM25:1;
      vuint32_t MBUFM24:1;
      vuint32_t MBUFM23:1;
      vuint32_t MBUFM22:1;
      vuint32_t MBUFM21:1;
      vuint32_t MBUFM20:1;
      vuint32_t MBUFM19:1;
      vuint32_t MBUFM18:1;
      vuint32_t MBUFM17:1;
      vuint32_t MBUFM16:1;
      vuint32_t MBUFM15:1;
      vuint32_t MBUFM14:1;
      vuint32_t MBUFM13:1;
      vuint32_t MBUFM12:1;
      vuint32_t MBUFM11:1;
      vuint32_t MBUFM10:1;
      vuint32_t MBUFM9:1;
      vuint32_t MBUFM8:1;
      vuint32_t MBUFM7:1;
      vuint32_t MBUFM6:1;
      vuint32_t MBUFM5:1;
      vuint32_t MBUFM4:1;
      vuint32_t MBUFM3:1;
      vuint32_t MBUFM2:1;
      vuint32_t MBUFM1:1;
      vuint32_t MBUFM0:1;
    } B;
  } MBUFML;

  union {                              /* STCU2 MBIST Unrecoverable FM Medium Register */
    vuint32_t R;
    struct {
      vuint32_t MBUFM63:1;
      vuint32_t MBUFM62:1;
      vuint32_t MBUFM61:1;
      vuint32_t MBUFM60:1;
      vuint32_t MBUFM59:1;
      vuint32_t MBUFM58:1;
      vuint32_t MBUFM57:1;
      vuint32_t MBUFM56:1;
      vuint32_t MBUFM55:1;
      vuint32_t MBUFM54:1;
      vuint32_t MBUFM53:1;
      vuint32_t MBUFM52:1;
      vuint32_t MBUFM51:1;
      vuint32_t MBUFM50:1;
      vuint32_t MBUFM49:1;
      vuint32_t MBUFM48:1;
      vuint32_t MBUFM47:1;
      vuint32_t MBUFM46:1;
      vuint32_t MBUFM45:1;
      vuint32_t MBUFM44:1;
      vuint32_t MBUFM43:1;
      vuint32_t MBUFM42:1;
      vuint32_t MBUFM41:1;
      vuint32_t MBUFM40:1;
      vuint32_t MBUFM39:1;
      vuint32_t MBUFM38:1;
      vuint32_t MBUFM37:1;
      vuint32_t MBUFM36:1;
      vuint32_t MBUFM35:1;
      vuint32_t MBUFM34:1;
      vuint32_t MBUFM33:1;
      vuint32_t MBUFM32:1;
    } B;
  } MBUFMM;

  union {                              /* STCU2 MBIST Unrecoverable FM High Register */
    vuint32_t R;
    struct {
      vuint32_t  :18;
      vuint32_t MBUFM77:1;
      vuint32_t MBUFM76:1;
      vuint32_t MBUFM75:1;
      vuint32_t MBUFM74:1;
      vuint32_t MBUFM73:1;
      vuint32_t MBUFM72:1;
      vuint32_t MBUFM71:1;
      vuint32_t MBUFM70:1;
      vuint32_t MBUFM69:1;
      vuint32_t MBUFM68:1;
      vuint32_t MBUFM67:1;
      vuint32_t MBUFM66:1;
      vuint32_t MBUFM65:1;
      vuint32_t MBUFM64:1;
    } B;
  } MBUFMH;

  uint8_t STCU2_reserved0[128];
  struct {
    union {                            /* STCU2 LBIST Control Register */
      vuint32_t R;
      struct {
        vuint32_t CSM:1;
        vuint32_t PTR:7;
        vuint32_t  :4;
        vuint32_t PRPGEN:1;
        vuint32_t SHS:3;
        vuint32_t SCEN_OFF:4;
        vuint32_t SCEN_ON:4;
        vuint32_t  :4;
        vuint32_t PFT:1;
        vuint32_t CWS:3;
      } B;
    } LB_CTRL;
    union {                            /* STCU2 LBIST PC Stop Register */
      vuint32_t R;
      struct {
        vuint32_t  :6;
        vuint32_t PCS:26;
      } B;
    } LB_PCS;
    union {                            /* STCU2 LBIST PRPG Low Register */
      vuint32_t R;
      struct {
        vuint32_t PRPGx:32;
      } B;
    } LB_PRPGL;
    union {                            /* STCU2 LBIST PRPG High Register */
      vuint32_t R;
      struct {
        vuint32_t PRPGx:32;
      } B;
    } LB_PRPGH;
    union {                            /* STCU2 Off-Line LBIST MISR Expected Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISREx:32;
      } B;
    } LB_MISREL;
    union {                            /* STCU2 Off-Line LBIST MISR Expected High Register */
      vuint32_t R;
      struct {
        vuint32_t MISREx:32;
      } B;
    } LB_MISREH;
    union {                            /* STCU2 Off-Line LBIST MISR Read Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRx:32;
      } B;
    } LB_MISRRL;
    union {                            /* STCU2 Off-Line LBIST MISR Read High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRx:32;
      } B;
    } LB_MISRRH;
    union {                            /* STCU2 On-Line LBIST MISR Expected Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRESWx:32;
      } B;
    } LB_MISRELSW;
    union {                            /* STCU2 On-Line LBIST MISR Expected High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRESWx:32;
      } B;
    } LB_MISREHSW;
    union {                            /* STCU2 On-Line LBIST MISR Read Low Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRSWx:32;
      } B;
    } LB_MISRRLSW;
    union {                            /* STCU2 On-Line LBIST MISR Read High Register */
      vuint32_t R;
      struct {
        vuint32_t MISRRSWx:32;
      } B;
    } LB_MISRRHSW;
    uint8_t LB_reserved0[16];
  } LB[10];

  uint8_t STCU2_reserved1[640];
  union {                              /* STCU2 MBIST Control Register */
    vuint32_t R;
    struct {
      vuint32_t CSM:1;
      vuint32_t PTR:7;
      vuint32_t  :24;
    } B;
  } MB_CTRL[78];
};


/* ============================================================================
   =============================== Module: STM ================================
   ============================================================================ */

struct STM_tag {
  union {                              /* STM Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t CPS:8;                 /* Counter Prescaler. */
      vuint32_t  :6;
      vuint32_t FRZ:1;                 /* Freeze. */
      vuint32_t TEN:1;                 /* Timer counter Enabled. */
    } B;
  } CR;

  union {                              /* STM Count Register */
    vuint32_t R;
    struct {
      vuint32_t CNT:32;                /* Timer count value used as the time base for all channels. */
    } B;
  } CNT;

  uint8_t STM_reserved0[8];
  struct {
    union {                            /* STM Channel Control Register */
      vuint32_t R;
      struct {
        vuint32_t  :31;
        vuint32_t CEN:1;               /* Channel Enable */
      } B;
    } CCR;
    union {                            /* STM Channel Interrupt Register */
      vuint32_t R;
      struct {
        vuint32_t  :31;
        vuint32_t CIF:1;               /* Channel Interrupt Flag */
      } B;
    } CIR;
    union {                            /* STM Channel Compare Register */
      vuint32_t R;
      struct {
        vuint32_t CMP:32;              /* Compare value for channel n. */
      } B;
    } CMP;
    uint8_t CHANNEL_reserved0[4];
  } CHANNEL[4];
};


/* ============================================================================
   =============================== Module: SWT ================================
   ============================================================================ */

struct SWT_tag {
  union {                              /* SWT Control Register */
    vuint32_t R;
    struct {
      vuint32_t MAP0:1;
      vuint32_t MAP1:1;
      vuint32_t MAP2:1;
      vuint32_t MAP3:1;
      vuint32_t MAP4:1;
      vuint32_t MAP5:1;
      vuint32_t MAP6:1;
      vuint32_t MAP7:1;
      vuint32_t  :13;
      vuint32_t SMD:2;                 /* Service Mode. */
      vuint32_t RIA:1;
      vuint32_t WND:1;
      vuint32_t ITR:1;
      vuint32_t HLK:1;
      vuint32_t SLK:1;
      vuint32_t  :1;                   /* Reserved. */
      vuint32_t STP:1;
      vuint32_t FRZ:1;
      vuint32_t WEN:1;
    } B;
  } CR;

  union {                              /* SWT Interrupt Register */
    vuint32_t R;
    struct {
      vuint32_t  :31;
      vuint32_t TIF:1;
    } B;
  } IR;

  union {                              /* SWT Time-out Register */
    vuint32_t R;
    struct {
      vuint32_t WTO:32;
    } B;
  } TO;

  union {                              /* SWT Window Register */
    vuint32_t R;
    struct {
      vuint32_t WST:32;
    } B;
  } WN;

  union {                              /* SWT Service Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t WSC:16;
    } B;
  } SR;

  union {                              /* SWT Counter Output Register */
    vuint32_t R;
    struct {
      vuint32_t CNT:32;
    } B;
  } CO;

  union {                              /* SWT Service Key Register */
    vuint32_t R;
    struct {
      vuint32_t  :16;
      vuint32_t SK:16;                 /* Service Key. */
    } B;
  } SK;
};


/* ============================================================================
   =============================== Module: TDM ================================
   ============================================================================ */

struct TDM_tag {
  union {                              /* TDR Status Register */
    vuint32_t R;
    struct {
      vuint32_t  :26;
      vuint32_t TDRSR5:1;
      vuint32_t TDRSR4:1;
      vuint32_t TDRSR3:1;
      vuint32_t TDRSR2:1;
      vuint32_t TDRSR1:1;
      vuint32_t TDRSR0:1;
    } B;
  } TDRSR;

  union {                              /* Last Flash Programmed Address Register */
    vuint32_t R;
    struct {
      vuint32_t  :8;
      vuint32_t LFPAR:24;
    } B;
  } LFPAR;

  union {                              /* Diary Base Address */
    vuint32_t R;
    struct {
      vuint32_t DBA:32;
    } B;
  } DBA;

  uint8_t TDM_reserved0[4];
  union {                              /* Software Tamper Override Key Region */
    vuint32_t R;
    struct {
      vuint32_t STO_KEY:32;
    } B;
  } STO_KEY[6];
};


/* ============================================================================
   =============================== Module: WKPU ===============================
   ============================================================================ */

struct WKPU_tag {
  union {                              /* NMI Status Flag Register */
    vuint32_t R;
    struct {
      vuint32_t NIF0:1;                /* NMI Status Flag 0 (safety core) */
      vuint32_t NOVF0:1;               /* NMI Overrun Status Flag 0 (safety core) */
      vuint32_t  :6;
      vuint32_t NIF1:1;                /* NMI Status Flag 1 (main core) */
      vuint32_t NOVF1:1;               /* NMI Overrun Status Flag 1 (main core) */
      vuint32_t  :6;
      vuint32_t NIF2:1;                /* NMI Status Flag 2 (IOP) */
      vuint32_t NOVF2:1;               /* NMI Overrun Status Flag 2 (IOP) */
      vuint32_t  :6;
      vuint32_t RIF:1;                 /* Reset Status Flag */
      vuint32_t ROVF:1;                /* Reset Overrun Status Flag */
      vuint32_t  :6;
    } B;
  } NSR;

  uint8_t WKPU_reserved0[4];
  union {                              /* NMI Configuration Register */
    vuint32_t R;
    struct {
      vuint32_t NLOCK0:1;              /* NMI Configuration Lock Register 0 */
      vuint32_t NDSS0:2;               /* NMI Destination Source Select 0 */
      vuint32_t NWRE0:1;               /* NMI Wakeup Request Enable 0 */
      vuint32_t  :1;
      vuint32_t NREE0:1;               /* NMI Rising-edge Events Enable 0 */
      vuint32_t NFEE0:1;               /* NMI Falling-edge Events Enable 0 */
      vuint32_t NFE0:1;                /* NMI Filter Enable */
      vuint32_t NLOCK1:1;              /* NMI Configuration Lock Register 1 */
      vuint32_t NDSS1:2;               /* NMI Destination Source Select 1 */
      vuint32_t NWRE1:1;               /* NMI Wakeup Request Enable 1 */
      vuint32_t  :1;
      vuint32_t NREE1:1;               /* NMI Rising-edge Events Enable 1 */
      vuint32_t NFEE1:1;               /* NMI Falling-edge Events Enable 1 */
      vuint32_t  :1;
      vuint32_t NLOCK2:1;              /* NMI Configuration Lock Register 2 */
      vuint32_t NDSS2:2;               /* NMI Destination Source Select 2 */
      vuint32_t NWRE2:1;               /* NMI Wakeup Request Enable 2 */
      vuint32_t  :1;
      vuint32_t NREE2:1;               /* NMI Rising-edge Events Enable 2 */
      vuint32_t NFEE2:1;               /* NMI Falling-edge Events Enable 2 */
      vuint32_t  :1;
      vuint32_t RLOCK:1;               /* Reset Configuration Lock Register */
      vuint32_t RDSS:2;                /* Reset Destination Source Select */
      vuint32_t RWRE:1;                /* Reset Wakeup Request Enable */
      vuint32_t  :1;
      vuint32_t RREE:1;                /* Reset Rising-edge Events Enable */
      vuint32_t RFEE:1;                /* Reset Falling-edge Events Enable */
      vuint32_t  :1;
    } B;
  } NCR;
};


/* ============================================================================
   =============================== Module: XBAR ===============================
   ============================================================================ */

struct XBAR_tag {
  struct {
    union {                            /* XBAR Priority Registers Slave */
      vuint32_t R;
      struct {
        vuint32_t  :1;
        vuint32_t M7:3;
        vuint32_t  :1;
        vuint32_t M6:3;
        vuint32_t  :1;
        vuint32_t M5:3;
        vuint32_t  :1;
        vuint32_t M4:3;
        vuint32_t  :1;
        vuint32_t M3:3;
        vuint32_t  :1;
        vuint32_t M2:3;
        vuint32_t  :1;
        vuint32_t M1:3;
        vuint32_t  :1;
        vuint32_t M0:3;
      } B;
    } PRS;
    uint8_t PORT_reserved0[12];
    union {                            /* XBAR Control Register */
      vuint32_t R;
      struct {
        vuint32_t RO:1;
        vuint32_t HRP:1;
        vuint32_t  :6;
        vuint32_t HPE7:1;
        vuint32_t HPE6:1;
        vuint32_t HPE5:1;
        vuint32_t HPE4:1;
        vuint32_t HPE3:1;
        vuint32_t HPE2:1;
        vuint32_t HPE1:1;
        vuint32_t HPE0:1;
        vuint32_t  :6;
        vuint32_t ARB:2;
        vuint32_t  :2;
        vuint32_t PCTL:2;
        vuint32_t  :1;
        vuint32_t PARK:3;
      } B;
    } CRS;
    uint8_t PORT_reserved1[236];
  } PORT[8];
};


/* ============================================================================
   =============================== Module: XBIC ===============================
   ============================================================================ */

struct XBIC_tag {
  union {                              /* XBIC Module Control Register */
    vuint32_t R;
    struct {
      vuint32_t SE0:1;
      vuint32_t SE1:1;
      vuint32_t SE2:1;
      vuint32_t SE3:1;
      vuint32_t SE4:1;
      vuint32_t SE5:1;
      vuint32_t SE6:1;
      vuint32_t SE7:1;
      vuint32_t ME0:1;
      vuint32_t ME1:1;
      vuint32_t ME2:1;
      vuint32_t ME3:1;
      vuint32_t ME4:1;
      vuint32_t ME5:1;
      vuint32_t ME6:1;
      vuint32_t ME7:1;
      vuint32_t  :16;
    } B;
  } MCR;

  union {                              /* XBIC Error Injection Register */
    vuint32_t R;
    struct {
      vuint32_t EIE:1;
      vuint32_t  :16;
      vuint32_t SLV:3;
      vuint32_t MST:4;
      vuint32_t SYN:8;
    } B;
  } EIR;

  union {                              /* XBIC Error Status Register */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t DPSE0:1;
      vuint32_t DPSE1:1;
      vuint32_t DPSE2:1;
      vuint32_t DPSE3:1;
      vuint32_t DPSE4:1;
      vuint32_t DPSE5:1;
      vuint32_t DPSE6:1;
      vuint32_t DPSE7:1;
      vuint32_t DPME0:1;
      vuint32_t DPME1:1;
      vuint32_t DPME2:1;
      vuint32_t DPME3:1;
      vuint32_t DPME4:1;
      vuint32_t DPME5:1;
      vuint32_t DPME6:1;
      vuint32_t DPME7:1;
      vuint32_t SLV:3;
      vuint32_t MST:4;
      vuint32_t SYN:8;
    } B;
  } ESR;

  union {                              /* XBIC Error Address Register */
    vuint32_t R;
    struct {
      vuint32_t ADDR:32;
    } B;
  } EAR;
};


/* ============================================================================
   =============================== Module: XOSC ===============================
   ============================================================================ */

struct XOSC_tag {
  union {                              /* XOSC Control Register */
    vuint32_t R;
    struct {
      vuint32_t OSCBYP:1;
      vuint32_t  :7;
      vuint32_t EOCV:8;                /* End of Count Value */
      vuint32_t M_OSC:1;               /* Crystal oscillator clock interrupt mask */
      vuint32_t  :2;
      vuint32_t  :5;
      vuint32_t I_OSC:1;
      vuint32_t  :5;
      vuint32_t  :1;
      vuint32_t  :1;
    } B;
  } CTL;
};


/* ============================================================================
   =============================== Module: eDMA ===============================
   ============================================================================ */

struct eDMA_tag {
  union {                              /* Control Register */
    vuint32_t R;
    struct {
      vuint32_t  :14;
      vuint32_t CX:1;
      vuint32_t ECX:1;
      vuint32_t GRP3PRI:2;
      vuint32_t GRP2PRI:2;
      vuint32_t GRP1PRI:2;
      vuint32_t GRP0PRI:2;
      vuint32_t EMLM:1;
      vuint32_t CLM:1;
      vuint32_t HALT:1;
      vuint32_t HOE:1;
      vuint32_t ERGA:1;
      vuint32_t ERCA:1;
      vuint32_t EDBG:1;
      vuint32_t  :1;
    } B;
  } CR;

  union {                              /* Error Status */
    vuint32_t R;
    struct {
      vuint32_t VLD:1;
      vuint32_t  :13;
      vuint32_t UCE:1;
      vuint32_t ECX:1;
      vuint32_t GPE:1;
      vuint32_t CPE:1;
      vuint32_t ERRCHN:6;
      vuint32_t SAE:1;
      vuint32_t SOE:1;
      vuint32_t DAE:1;
      vuint32_t DOE:1;
      vuint32_t NCE:1;
      vuint32_t SGE:1;
      vuint32_t SBE:1;
      vuint32_t DBE:1;
    } B;
  } ES;

  union {                              /* Enable Request Register High */
    vuint32_t R;
    struct {
      vuint32_t ERQ63:1;
      vuint32_t ERQ62:1;
      vuint32_t ERQ61:1;
      vuint32_t ERQ60:1;
      vuint32_t ERQ59:1;
      vuint32_t ERQ58:1;
      vuint32_t ERQ57:1;
      vuint32_t ERQ56:1;
      vuint32_t ERQ55:1;
      vuint32_t ERQ54:1;
      vuint32_t ERQ53:1;
      vuint32_t ERQ52:1;
      vuint32_t ERQ51:1;
      vuint32_t ERQ50:1;
      vuint32_t ERQ49:1;
      vuint32_t ERQ48:1;
      vuint32_t ERQ47:1;
      vuint32_t ERQ46:1;
      vuint32_t ERQ45:1;
      vuint32_t ERQ44:1;
      vuint32_t ERQ43:1;
      vuint32_t ERQ42:1;
      vuint32_t ERQ41:1;
      vuint32_t ERQ40:1;
      vuint32_t ERQ39:1;
      vuint32_t ERQ38:1;
      vuint32_t ERQ37:1;
      vuint32_t ERQ36:1;
      vuint32_t ERQ35:1;
      vuint32_t ERQ34:1;
      vuint32_t ERQ33:1;
      vuint32_t ERQ32:1;
    } B;
  } ERQH;

  union {                              /* Enable Request Register Low */
    vuint32_t R;
    struct {
      vuint32_t ERQ31:1;
      vuint32_t ERQ30:1;
      vuint32_t ERQ29:1;
      vuint32_t ERQ28:1;
      vuint32_t ERQ27:1;
      vuint32_t ERQ26:1;
      vuint32_t ERQ25:1;
      vuint32_t ERQ24:1;
      vuint32_t ERQ23:1;
      vuint32_t ERQ22:1;
      vuint32_t ERQ21:1;
      vuint32_t ERQ20:1;
      vuint32_t ERQ19:1;
      vuint32_t ERQ18:1;
      vuint32_t ERQ17:1;
      vuint32_t ERQ16:1;
      vuint32_t ERQ15:1;
      vuint32_t ERQ14:1;
      vuint32_t ERQ13:1;
      vuint32_t ERQ12:1;
      vuint32_t ERQ11:1;
      vuint32_t ERQ10:1;
      vuint32_t ERQ9:1;
      vuint32_t ERQ8:1;
      vuint32_t ERQ7:1;
      vuint32_t ERQ6:1;
      vuint32_t ERQ5:1;
      vuint32_t ERQ4:1;
      vuint32_t ERQ3:1;
      vuint32_t ERQ2:1;
      vuint32_t ERQ1:1;
      vuint32_t ERQ0:1;
    } B;
  } ERQL;

  union {                              /* Enable Error Interrupt Register High */
    vuint32_t R;
    struct {
      vuint32_t EEI63:1;
      vuint32_t EEI62:1;
      vuint32_t EEI61:1;
      vuint32_t EEI60:1;
      vuint32_t EEI59:1;
      vuint32_t EEI58:1;
      vuint32_t EEI57:1;
      vuint32_t EEI56:1;
      vuint32_t EEI55:1;
      vuint32_t EEI54:1;
      vuint32_t EEI53:1;
      vuint32_t EEI52:1;
      vuint32_t EEI51:1;
      vuint32_t EEI50:1;
      vuint32_t EEI49:1;
      vuint32_t EEI48:1;
      vuint32_t EEI47:1;
      vuint32_t EEI46:1;
      vuint32_t EEI45:1;
      vuint32_t EEI44:1;
      vuint32_t EEI43:1;
      vuint32_t EEI42:1;
      vuint32_t EEI41:1;
      vuint32_t EEI40:1;
      vuint32_t EEI39:1;
      vuint32_t EEI38:1;
      vuint32_t EEI37:1;
      vuint32_t EEI36:1;
      vuint32_t EEI35:1;
      vuint32_t EEI34:1;
      vuint32_t EEI33:1;
      vuint32_t EEI32:1;
    } B;
  } EEIH;

  union {                              /* Enable Error Interrupt Register Low */
    vuint32_t R;
    struct {
      vuint32_t EEI31:1;
      vuint32_t EEI30:1;
      vuint32_t EEI29:1;
      vuint32_t EEI28:1;
      vuint32_t EEI27:1;
      vuint32_t EEI26:1;
      vuint32_t EEI25:1;
      vuint32_t EEI24:1;
      vuint32_t EEI23:1;
      vuint32_t EEI22:1;
      vuint32_t EEI21:1;
      vuint32_t EEI20:1;
      vuint32_t EEI19:1;
      vuint32_t EEI18:1;
      vuint32_t EEI17:1;
      vuint32_t EEI16:1;
      vuint32_t EEI15:1;
      vuint32_t EEI14:1;
      vuint32_t EEI13:1;
      vuint32_t EEI12:1;
      vuint32_t EEI11:1;
      vuint32_t EEI10:1;
      vuint32_t EEI9:1;
      vuint32_t EEI8:1;
      vuint32_t EEI7:1;
      vuint32_t EEI6:1;
      vuint32_t EEI5:1;
      vuint32_t EEI4:1;
      vuint32_t EEI3:1;
      vuint32_t EEI2:1;
      vuint32_t EEI1:1;
      vuint32_t EEI0:1;
    } B;
  } EEIL;

  union {                              /* Set Enable Request Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t SAER:1;
      vuint8_t SERQ:6;
    } B;
  } SERQ;

  union {                              /* Clear Enable Request Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAER:1;
      vuint8_t CERQ:6;
    } B;
  } CERQ;

  union {                              /* Set Enable Error Interrupt Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t SAEE:1;
      vuint8_t SEEI:6;
    } B;
  } SEEI;

  union {                              /* Clear Enable Error Interrupt Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAEE:1;
      vuint8_t CEEI:6;
    } B;
  } CEEI;

  union {                              /* Clear Interrupt Request Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAIR:1;
      vuint8_t CINT:6;
    } B;
  } CINT;

  union {                              /* Clear Error Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CAEI:1;
      vuint8_t CERR:6;
    } B;
  } CERR;

  union {                              /* Set START Bit Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t SAST:1;
      vuint8_t SSRT:6;
    } B;
  } SSRT;

  union {                              /* Clear DONE Status Bit Register */
    vuint8_t R;
    struct {
      vuint8_t NOP:1;
      vuint8_t CADN:1;
      vuint8_t CDNE:6;
    } B;
  } CDNE;

  union {                              /* Interrupt Request Register High */
    vuint32_t R;
    struct {
      vuint32_t INT63:1;
      vuint32_t INT62:1;
      vuint32_t INT61:1;
      vuint32_t INT60:1;
      vuint32_t INT59:1;
      vuint32_t INT58:1;
      vuint32_t INT57:1;
      vuint32_t INT56:1;
      vuint32_t INT55:1;
      vuint32_t INT54:1;
      vuint32_t INT53:1;
      vuint32_t INT52:1;
      vuint32_t INT51:1;
      vuint32_t INT50:1;
      vuint32_t INT49:1;
      vuint32_t INT48:1;
      vuint32_t INT47:1;
      vuint32_t INT46:1;
      vuint32_t INT45:1;
      vuint32_t INT44:1;
      vuint32_t INT43:1;
      vuint32_t INT42:1;
      vuint32_t INT41:1;
      vuint32_t INT40:1;
      vuint32_t INT39:1;
      vuint32_t INT38:1;
      vuint32_t INT37:1;
      vuint32_t INT36:1;
      vuint32_t INT35:1;
      vuint32_t INT34:1;
      vuint32_t INT33:1;
      vuint32_t INT32:1;
    } B;
  } INTH;

  union {                              /* Interrupt Request Register Low */
    vuint32_t R;
    struct {
      vuint32_t INT31:1;
      vuint32_t INT30:1;
      vuint32_t INT29:1;
      vuint32_t INT28:1;
      vuint32_t INT27:1;
      vuint32_t INT26:1;
      vuint32_t INT25:1;
      vuint32_t INT24:1;
      vuint32_t INT23:1;
      vuint32_t INT22:1;
      vuint32_t INT21:1;
      vuint32_t INT20:1;
      vuint32_t INT19:1;
      vuint32_t INT18:1;
      vuint32_t INT17:1;
      vuint32_t INT16:1;
      vuint32_t INT15:1;
      vuint32_t INT14:1;
      vuint32_t INT13:1;
      vuint32_t INT12:1;
      vuint32_t INT11:1;
      vuint32_t INT10:1;
      vuint32_t INT9:1;
      vuint32_t INT8:1;
      vuint32_t INT7:1;
      vuint32_t INT6:1;
      vuint32_t INT5:1;
      vuint32_t INT4:1;
      vuint32_t INT3:1;
      vuint32_t INT2:1;
      vuint32_t INT1:1;
      vuint32_t INT0:1;
    } B;
  } INTL;

  union {                              /* Error Register High */
    vuint32_t R;
    struct {
      vuint32_t ERR63:1;
      vuint32_t ERR62:1;
      vuint32_t ERR61:1;
      vuint32_t ERR60:1;
      vuint32_t ERR59:1;
      vuint32_t ERR58:1;
      vuint32_t ERR57:1;
      vuint32_t ERR56:1;
      vuint32_t ERR55:1;
      vuint32_t ERR54:1;
      vuint32_t ERR53:1;
      vuint32_t ERR52:1;
      vuint32_t ERR51:1;
      vuint32_t ERR50:1;
      vuint32_t ERR49:1;
      vuint32_t ERR48:1;
      vuint32_t ERR47:1;
      vuint32_t ERR46:1;
      vuint32_t ERR45:1;
      vuint32_t ERR44:1;
      vuint32_t ERR43:1;
      vuint32_t ERR42:1;
      vuint32_t ERR41:1;
      vuint32_t ERR40:1;
      vuint32_t ERR39:1;
      vuint32_t ERR38:1;
      vuint32_t ERR37:1;
      vuint32_t ERR36:1;
      vuint32_t ERR35:1;
      vuint32_t ERR34:1;
      vuint32_t ERR33:1;
      vuint32_t ERR32:1;
    } B;
  } ERRH;

  union {                              /* Error Register Low */
    vuint32_t R;
    struct {
      vuint32_t ERR31:1;
      vuint32_t ERR30:1;
      vuint32_t ERR29:1;
      vuint32_t ERR28:1;
      vuint32_t ERR27:1;
      vuint32_t ERR26:1;
      vuint32_t ERR25:1;
      vuint32_t ERR24:1;
      vuint32_t ERR23:1;
      vuint32_t ERR22:1;
      vuint32_t ERR21:1;
      vuint32_t ERR20:1;
      vuint32_t ERR19:1;
      vuint32_t ERR18:1;
      vuint32_t ERR17:1;
      vuint32_t ERR16:1;
      vuint32_t ERR15:1;
      vuint32_t ERR14:1;
      vuint32_t ERR13:1;
      vuint32_t ERR12:1;
      vuint32_t ERR11:1;
      vuint32_t ERR10:1;
      vuint32_t ERR9:1;
      vuint32_t ERR8:1;
      vuint32_t ERR7:1;
      vuint32_t ERR6:1;
      vuint32_t ERR5:1;
      vuint32_t ERR4:1;
      vuint32_t ERR3:1;
      vuint32_t ERR2:1;
      vuint32_t ERR1:1;
      vuint32_t ERR0:1;
    } B;
  } ERRL;

  union {                              /* Hardware Request Status Register High */
    vuint32_t R;
    struct {
      vuint32_t HRS63:1;
      vuint32_t HRS62:1;
      vuint32_t HRS61:1;
      vuint32_t HRS60:1;
      vuint32_t HRS59:1;
      vuint32_t HRS58:1;
      vuint32_t HRS57:1;
      vuint32_t HRS56:1;
      vuint32_t HRS55:1;
      vuint32_t HRS54:1;
      vuint32_t HRS53:1;
      vuint32_t HRS52:1;
      vuint32_t HRS51:1;
      vuint32_t HRS50:1;
      vuint32_t HRS49:1;
      vuint32_t HRS48:1;
      vuint32_t HRS47:1;
      vuint32_t HRS46:1;
      vuint32_t HRS45:1;
      vuint32_t HRS44:1;
      vuint32_t HRS43:1;
      vuint32_t HRS42:1;
      vuint32_t HRS41:1;
      vuint32_t HRS40:1;
      vuint32_t HRS39:1;
      vuint32_t HRS38:1;
      vuint32_t HRS37:1;
      vuint32_t HRS36:1;
      vuint32_t HRS35:1;
      vuint32_t HRS34:1;
      vuint32_t HRS33:1;
      vuint32_t HRS32:1;
    } B;
  } HRSH;

  union {                              /* Hardware Request Status Register Low */
    vuint32_t R;
    struct {
      vuint32_t HRS31:1;
      vuint32_t HRS30:1;
      vuint32_t HRS29:1;
      vuint32_t HRS28:1;
      vuint32_t HRS27:1;
      vuint32_t HRS26:1;
      vuint32_t HRS25:1;
      vuint32_t HRS24:1;
      vuint32_t HRS23:1;
      vuint32_t HRS22:1;
      vuint32_t HRS21:1;
      vuint32_t HRS20:1;
      vuint32_t HRS19:1;
      vuint32_t HRS18:1;
      vuint32_t HRS17:1;
      vuint32_t HRS16:1;
      vuint32_t HRS15:1;
      vuint32_t HRS14:1;
      vuint32_t HRS13:1;
      vuint32_t HRS12:1;
      vuint32_t HRS11:1;
      vuint32_t HRS10:1;
      vuint32_t HRS9:1;
      vuint32_t HRS8:1;
      vuint32_t HRS7:1;
      vuint32_t HRS6:1;
      vuint32_t HRS5:1;
      vuint32_t HRS4:1;
      vuint32_t HRS3:1;
      vuint32_t HRS2:1;
      vuint32_t HRS1:1;
      vuint32_t HRS0:1;
    } B;
  } HRSL;

  uint8_t eDMA_reserved0[200];
  union {                              /* Channel Priority Register */
    vuint8_t R;
    struct {
      vuint8_t ECP:1;
      vuint8_t DPA:1;
      vuint8_t GRPPRI:2;
      vuint8_t CHPRI:4;
    } B;
  } DCHPRI[64];

  union {                              /* Channel Master ID Register */
    vuint8_t R;
    struct {
      vuint8_t EMI:1;
      vuint8_t PAL:1;
      vuint8_t  :2;
      vuint8_t MID:4;
    } B;
  } DCHMID[64];

  uint8_t eDMA_reserved1[3712];
/*! >>>>> v1.0_issue - TCD header file structures / unions have changed <<<<< */
  
// to use new TCD definition, include this section
#if 0
  struct {
    union {                            /* TCD Source Address */
      vuint32_t R;
      struct {
        vuint32_t SADDR:32;
      } B;
    } SADDR;
    union {                            /* TCD Transfer Attributes */
      vuint16_t R;
      struct {
        vuint16_t SMOD:5;
        vuint16_t SSIZE:3;
        vuint16_t DMOD:5;
        vuint16_t DSIZE:3;
      } B;
    } ATTR;
    union {                            /* TCD Signed Source Address Offset */
      vuint16_t R;
      struct {
        vuint16_t SOFF:16;
      } B;
    } SOFF;
    union {
      union {                          /* TCD Minor Byte Count Minor Loop Disabled */
        vuint32_t R;
        struct {
          vuint32_t NBYTES:32;
        } B;
      } MLNO;
      union {                          /* TCD Signed Minor Loop Offset Minor Loop Enabled and Offset Disabled */
        vuint32_t R;
        struct {
          vuint32_t SMLOE:1;
          vuint32_t DMLOE:1;
          vuint32_t NBYTES:30;
        } B;
      } MLOFFNO;
      union {                          /* TCD Signed Minor Loop Offset Minor Loop and Offset Enabled */
        vuint32_t R;
        struct {
          vuint32_t SMLOE:1;
          vuint32_t DMLOE:1;
          vuint32_t MLOFF:20;
          vuint32_t NBYTES:10;
        } B;
      } MLOFFYES;
    } NBYTES;
    union {                            /* TCD Last Source Address Adjustment */
      vuint32_t R;
      struct {
        vuint32_t SLAST:32;
      } B;
    } SLAST;
    union {                            /* TCD Destination Address */
      vuint32_t R;
      struct {
        vuint32_t DADDR:32;
      } B;
    } DADDR;
    union {
      union {                          /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Disabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t CITER:15;
        } B;
      } ELINKNO;
      union {                          /* TCD Current Minor Loop Link, Major Loop Count Channel Linking Enabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t LINKCH:6;
          vuint16_t CITER:9;
        } B;
      } ELINKYES;
    } CITER;
    union {                            /* TCD Signed Destination Address Offset */
      vuint16_t R;
      struct {
        vuint16_t DOFF:16;
      } B;
    } DOFF;
    union {                            /* TCD Last Destination Address Adjustment/Scatter Gather Address */
      vuint32_t R;
      struct {
        vuint32_t DLASTSGA:32;
      } B;
    } DLASTSGA;
    union {
      union {                          /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Disabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t BITER:15;
        } B;
      } ELINKNO;
      union {                          /* TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled */
        vuint16_t R;
        struct {
          vuint16_t ELINK:1;
          vuint16_t LINKCH:6;
          vuint16_t BITER:9;
        } B;
      } ELINKYES;
    } BITER;
    union {                            /* TCD Control and Status */
      vuint16_t R;
      struct {
        vuint16_t BWC:2;
        vuint16_t MAJORLINKCH:6;
        vuint16_t DONE:1;
        vuint16_t ACTIVE:1;
        vuint16_t MAJORELINK:1;
        vuint16_t ESG:1;
        vuint16_t DREQ:1;
        vuint16_t INTHALF:1;
        vuint16_t INTMAJOR:1;
        vuint16_t START:1;
      } B;
    } CSR;
  } TCD[64];
};
#endif 
#if 1

/****************************************************************************/
/*       DMA Transfer Control Descriptor                                  */
/****************************************************************************/

        struct tcd_t {          /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */
            vuint32_t SADDR;    /* source address */

            vuint16_t SMOD:5;   /* source address modulo */
            vuint16_t SSIZE:3;  /* source transfer size */
            vuint16_t DMOD:5;   /* destination address modulo */
            vuint16_t DSIZE:3;  /* destination transfer size */
            vint16_t SOFF;      /* signed source address offset */

            vuint32_t NBYTES;   /* inner (minor) byte count */
            //vuint32_t NBYTES:32;    /* MLNO */
            // vuint32_t SMLOE:1;         /* MLNOFFNO */
            // vuint32_t DMLOE:1;
            // vuint32_t NBYTES:30;
            // vuint32_t SMLOE:1;         /* MLNOFFYES */
            // vuint32_t DMLOE:1;
            // vuint32_t MLOFF: 20;
            // vuint32_t NBYTES:10;

            vint32_t SLAST;     /* last destination address adjustment, or

                                   scatter/gather address (if e_sg = 1) */
            vuint32_t DADDR;    /* destination address */

            vuint16_t CITER_ELINK:1;    /* ELINK yes */
            vuint16_t CITER_LINKCH:6;
            vuint16_t CITER:9;
            // vuint16_t ELINK:1;         /* ELINK no */
            // vuint16_t CITER:15;

            vint16_t DOFF;      /* signed destination address offset */

            vint32_t DLAST_SGA;

            vuint16_t BITER_ELINK:1;    /* ELINK yes */
            vuint16_t BITER_LINKCH:6;
            vuint16_t BITER:9;
            // vuint16_t ELINK:1;         /* ELINK no */
            // vuint16_t BITER:15;

            vuint16_t BWC:2;    /* bandwidth control */
            vuint16_t MAJORLINKCH:6;    /* enable channel-to-channel link */
            vuint16_t DONE:1;   /* channel done */
            vuint16_t ACTIVE:1; /* channel active */
            vuint16_t MAJORELINK:1;     /* enable channel-to-channel link */
            vuint16_t ESG:1;    /* enable scatter/gather descriptor */
            vuint16_t DREQ:1;   /* disable ipd_req when done */
            vuint16_t INTHALF:1;        /* interrupt on citer = (biter >> 1) */
            vuint16_t INTMAJ:1; /* interrupt on major loop completion */
            vuint16_t START:1;  /* explicit channel start */

        } TCD[64];              /* transfer_control_descriptor */
    };

#endif

#define SRAM0_START 0x40000000UL;
#define AMU2 (*(volatile struct AMU2_tag *) 0xFC0D0000UL)
#define C55FMC (*(volatile struct C55FMC_tag *) 0xFFFE0000UL)
#define CMU_ADCSAR (*(volatile struct CMU_tag *) 0xFBFB0340UL)
#define CMU_ADCSD (*(volatile struct CMU_tag *) 0xFBFB0300UL)
#define CMU_CLKOUT (*(volatile struct CMU_tag *) 0xFBFB04C0UL)
#define CMU_CORE (*(volatile struct CMU_tag *) 0xFBFB0480UL)
#define CMU_FXBAR (*(volatile struct CMU_tag *) 0xFBFB0200UL)
#define CMU_PBRIDGE (*(volatile struct CMU_tag *) 0xFBFB0280UL)
#define CMU_PER (*(volatile struct CMU_tag *) 0xFBFB02C0UL)
#define CMU_PLL (*(volatile struct CMU_tag *) 0xFFFB0200UL)
#define CMU_PSI5_1US (*(volatile struct CMU_tag *) 0xFBFB0440UL)
#define CMU_PSI5_F125 (*(volatile struct CMU_tag *) 0xFBFB0400UL)
#define CMU_PSI5_F189 (*(volatile struct CMU_tag *) 0xFBFB03C0UL)
#define CMU_SENT (*(volatile struct CMU_tag *) 0xFBFB0380UL)
#define CMU_SXBAR (*(volatile struct CMU_tag *) 0xFBFB0240UL)
#define CRC_0 (*(volatile struct CRC_tag *) 0xFFF64000UL)
#define CRC_1 (*(volatile struct CRC_tag *) 0xFBF64000UL)
//! >>>>> v1.0_issue module name changed from DMACHMUX_n to DMAMUX_n.  Reference manual v2 shows DMACHMUX, RM v3 shows DMAMUX
#if 0
#define DMAMUX_0 (*(volatile struct DMAMUX_tag *) 0xFFF6C000UL)
#define DMAMUX_1 (*(volatile struct DMAMUX_tag *) 0xFFF6C200UL)
#define DMAMUX_2 (*(volatile struct DMAMUX_tag *) 0xFFF6C400UL)
#define DMAMUX_3 (*(volatile struct DMAMUX_tag *) 0xFFF6C600UL)
#define DMAMUX_4 (*(volatile struct DMAMUX_tag *) 0xFFF6C800UL)
#define DMAMUX_5 (*(volatile struct DMAMUX_tag *) 0xFFF6CA00UL)
#define DMAMUX_6 (*(volatile struct DMAMUX_tag *) 0xFFF6CC00UL)
#define DMAMUX_7 (*(volatile struct DMAMUX_tag *) 0xFFF6CE00UL)
#define DMAMUX_8 (*(volatile struct DMAMUX_tag *) 0xFFF6D000UL)
#define DMAMUX_9 (*(volatile struct DMAMUX_tag *) 0xFFF6D200UL)
#endif
#if 1
#define DMACHMUX_0 (*(volatile struct DMAMUX_tag *) 0xFFF6C000UL)
#define DMACHMUX_1 (*(volatile struct DMAMUX_tag *) 0xFFF6C200UL)
#define DMACHMUX_2 (*(volatile struct DMAMUX_tag *) 0xFFF6C400UL)
#define DMACHMUX_3 (*(volatile struct DMAMUX_tag *) 0xFFF6C600UL)
#define DMACHMUX_4 (*(volatile struct DMAMUX_tag *) 0xFFF6C800UL)
#define DMACHMUX_5 (*(volatile struct DMAMUX_tag *) 0xFFF6CA00UL)
#define DMACHMUX_6 (*(volatile struct DMAMUX_tag *) 0xFFF6CC00UL)
#define DMACHMUX_7 (*(volatile struct DMAMUX_tag *) 0xFFF6CE00UL)
#define DMACHMUX_8 (*(volatile struct DMAMUX_tag *) 0xFFF6D000UL)
#define DMACHMUX_9 (*(volatile struct DMAMUX_tag *) 0xFFF6D200UL)
#endif
#define DSPI_0 (*(volatile struct DSPI_tag *) 0xFFE70000UL)
#define DSPI_1 (*(volatile struct DSPI_tag *) 0xFFE74000UL)
#define DSPI_12 (*(volatile struct DSPI_tag *) 0xFFE88000UL)
#define DSPI_2 (*(volatile struct DSPI_tag *) 0xFBE70000UL)
#define DSPI_3 (*(volatile struct DSPI_tag *) 0xFBE74000UL)
#define DSPI_4 (*(volatile struct DSPI_tag *) 0xFFE78000UL)
#define DSPI_5 (*(volatile struct DSPI_tag *) 0xFBE78000UL)
#define DSPI_6 (*(volatile struct DSPI_tag *) 0xFFE7C000UL)
#define DTS (*(volatile struct DTS_tag *) 0xFFF38000UL)
#define EBI (*(volatile struct EBI_tag *) 0xFFFF0000UL)
#define FCCU (*(volatile struct FCCU_tag *) 0xFBF58000UL)
#define FEC (*(volatile struct FEC_tag *) 0xFC0B0000UL)
#define FR_0 (*(volatile struct FR_tag *) 0xFFE50000UL)
#define FR_1 (*(volatile struct FR_tag *) 0xFBE50000UL)
#define GTMINT (*(volatile struct GTMINT_tag *) 0xFFD00000UL)
#define I2C_0 (*(volatile struct I2C_tag *) 0xFFE68000UL)
#define I2C_1 (*(volatile struct I2C_tag *) 0xFBE68000UL)
#define IMA (*(volatile struct IMA_tag *) 0xFFF54000UL)
//#define INTC_0 (*(volatile struct INTC_tag *) 0xFC040000UL)
#define INTC (*(volatile struct INTC_tag *) 0xFC040000UL)
#define IRCOSC (*(volatile struct IRCOSC_tag *) 0xFFFB0000UL)
#define JDC (*(volatile struct JDC_tag *) 0xFFF3C000UL)
#define JTAGM (*(volatile struct JTAGM_tag *) 0xFFF48000UL)
#define LFAST_0 (*(volatile struct LFAST_tag *) 0xFFFD8000UL)
#define LFAST_1 (*(volatile struct LFAST_tag *) 0xFFFDC000UL)
#define LINFlexD_0 (*(volatile struct LINFLEX_tag *) 0xFFE8C000UL)
#define LINFlexD_1 (*(volatile struct LINFLEX_tag *) 0xFFE90000UL)
#define LINFlexD_14 (*(volatile struct LINFLEX_tag *) 0xFFEA8000UL)
#define LINFlexD_15 (*(volatile struct LINFLEX_tag *) 0xFBEA8000UL)
#define LINFlexD_16 (*(volatile struct LINFLEX_tag *) 0xFFEAC000UL)
#define LINFlexD_2 (*(volatile struct LINFLEX_tag *) 0xFBE8C000UL)
#define MC_CGM (*(volatile struct MC_CGM_tag *) 0xFFFB0000UL)  // *** v1.0_issue - manually fixed error in base address for MC_CGM

#define MC_ME (*(volatile struct MC_ME_tag *) 0xFFFB8000UL)
#define MC_PCU (*(volatile struct MC_PCU_tag *) 0xFFFA0000UL)
#define MC_RGM (*(volatile struct MC_RGM_tag *) 0xFFFA8000UL)
#define MEMU (*(volatile struct MEMU_tag *) 0xFFF50000UL)
#define M_CAN_1 (*(volatile struct M_CAN_tag *) 0xFFEE4000UL)
#define M_CAN_2 (*(volatile struct M_CAN_tag *) 0xFFEE8000UL)
#define M_CAN_3 (*(volatile struct M_CAN_tag *) 0xFFEEC000UL)
#define M_CAN_4 (*(volatile struct M_CAN_tag *) 0xFFEF0000UL)
#define M_TTCAN (*(volatile struct M_TTCAN_tag *) 0xFFEDC000UL)
#define PASS (*(volatile struct PASS_tag *) 0xFFFF4000UL)
#define PBRIDGE_A (*(volatile struct PBRIDGE_tag *) 0xFC000000UL)
#define PBRIDGE_B (*(volatile struct PBRIDGE_tag *) 0xF8000000UL)
#define PCM (*(volatile struct PCM_tag *) 0xFC028000UL)
#define PFLASH (*(volatile struct PFLASH_tag *) 0xFC030000UL)
#define PIT_0 (*(volatile struct PIT_tag *) 0xFFF84000UL)
#define PIT PIT_0
#define PIT_1 (*(volatile struct PIT_tag *) 0xFFF80000UL)
#define PLLDIG (*(volatile struct PLLDIG_tag *) 0xFFFB0100UL)
#define PMCDIG (*(volatile struct PMCDIG_tag *) 0xFFFA0400UL)
#define PRAMC (*(volatile struct PRAMC_tag *) 0xFC020000UL)
#define PSI5_0 (*(volatile struct PSI5_tag *) 0xFFE40000UL)
#define PSI5_1 (*(volatile struct PSI5_tag *) 0xFBE40000UL)
#define PSI5S (*(volatile struct PSI5S_tag *) 0xFBF74000UL)
#define REG_PROT (*(volatile struct REG_PROT_tag *) 0UL)
#define SARADC_0 (*(volatile struct SARADC_tag *) 0xFFE00000UL)
#define SARADC_1 (*(volatile struct SARADC_tag *) 0xFBE04000UL)
#define SARADC_10 (*(volatile struct SARADC_tag *) 0xFBE28000UL)
#define SARADC_2 (*(volatile struct SARADC_tag *) 0xFBE08000UL)
#define SARADC_3 (*(volatile struct SARADC_tag *) 0xFBE0C000UL)
#define SARADC_4 (*(volatile struct SARADC_tag *) 0xFFE10000UL)
#define SARADC_5 (*(volatile struct SARADC_tag *) 0xFBE14000UL)  //! >>>>> v1.0_issue missing SARADC_5 <<<<<
#define SARADC_6 (*(volatile struct SARADC_tag *) 0xFBE18000UL)
#define SARADC_7 (*(volatile struct SARADC_tag *) 0xFBE1C000UL)
#define SARADC_8 (*(volatile struct SARADC_tag *) 0xFBE20000UL)
#define SARADC_9 (*(volatile struct SARADC_tag *) 0xFBE24000UL)
#define SARADC_B (*(volatile struct SARADC_tag *) 0xFFE3C000UL)
#define SDADC_0 (*(volatile struct SDADC_tag *) 0xFFF0C000UL)
#define SDADC_1 (*(volatile struct SDADC_tag *) 0xFBF0C000UL)
#define SDADC_2 (*(volatile struct SDADC_tag *) 0xFFF10000UL)
#define SDADC_3 (*(volatile struct SDADC_tag *) 0xFBF10000UL)
#define SDADC_4 (*(volatile struct SDADC_tag *) 0xFFF14000UL)
#define SDADC_5 (*(volatile struct SDADC_tag *) 0xFBF14000UL)
#define SDADC_6 (*(volatile struct SDADC_tag *) 0xFFF18000UL)
#define SDADC_7 (*(volatile struct SDADC_tag *) 0xFBF18000UL)
#define SDADC_8 (*(volatile struct SDADC_tag *) 0xFFF1C000UL)
#define SDADC_9 (*(volatile struct SDADC_tag *) 0xFBF1C000UL)
#define SEMA42 (*(volatile struct SEMA42_tag *) 0xFC03C000UL)
#define SIPI_0 (*(volatile struct SIPI_tag *) 0xFFFD0000UL)
#define SIPI_1 (*(volatile struct SIPI_tag *) 0xFFFD4000UL)
#define SIUL2 (*(volatile struct SIUL2_tag *) 0xFFFC0000UL)
#define SIU SIUL2
#define SMPU_0 (*(volatile struct SMPU_tag *) 0xFC010000UL)
#define SMPU_1 (*(volatile struct SMPU_tag *) 0xFC014000UL)
#define SRX_0 (*(volatile struct SRX_tag *) 0xFFE5C000UL)
#define SRX_1 (*(volatile struct SRX_tag *) 0xFBE5C000UL)
#define SSCM (*(volatile struct SSCM_tag *) 0xFFFF8000UL)
#define STCU2 (*(volatile struct STCU2_tag *) 0xFFF44000UL)
#define STM_0 (*(volatile struct STM_tag *) 0xFC068000UL)
#define STM_1 (*(volatile struct STM_tag *) 0xFC06C000UL)
#define STM_2 (*(volatile struct STM_tag *) 0xFC070000UL)
#define SWT_0 (*(volatile struct SWT_tag *) 0xFC050000UL)
#define SWT_1 (*(volatile struct SWT_tag *) 0xFC054000UL)
#define SWT_2 (*(volatile struct SWT_tag *) 0xFC058000UL)
#define SWT_3 (*(volatile struct SWT_tag *) 0xFC05C000UL)
#define TDM (*(volatile struct TDM_tag *) 0xFFF34000UL)
#define WKPU (*(volatile struct WKPU_tag *) 0xFFF98000UL)
#define XBAR_0 (*(volatile struct XBAR_tag *) 0xFC004000UL)
#define XBAR_1 (*(volatile struct XBAR_tag *) 0xFC008000UL)
#define XBIC_0 (*(volatile struct XBIC_tag *) 0xFC018000UL)
#define XBIC_1 (*(volatile struct XBIC_tag *) 0xFC01C000UL)
#define XOSC (*(volatile struct XOSC_tag *) 0xFFFB0080UL)
//! >>>>> v1.0_issue eDMA name change from DMA <<<<< 
//#define eDMA_0 (*(volatile struct eDMA_tag *) 0xFC0A0000UL)
//#define eDMA_1 (*(volatile struct eDMA_tag *) 0xFC0A4000UL)
#define DMA_0 (*(volatile struct eDMA_tag *) 0xFC0A0000UL)
#define DMA_1 (*(volatile struct eDMA_tag *) 0xFC0A4000UL)


#ifdef __MWERKS__
#pragma pop
#endif
#ifdef __ghs__
#pragma ghs endnowarning
#endif
#ifdef  __cplusplus
}
#endif
#endif /* ifdef _MPC5777M_H */
